Gated Device Array Fabrication via Selective Trench Etching
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Solution Overview
Problem
The complexity of fabricating gated devices in semiconductor fabrication processes leads to increased costs, reduced throughput, and risks of misalignment or errors, particularly in forming arrays of memory cells.
Innovation Solution
A method of forming an array of gated devices involves creating trenches in a semiconductor substrate, filling them with dielectric material, and using ion implantation and diffusion to form doped regions, with a gate dielectric and conductive gate material formed laterally within the trenches, and selectively etching to form gate lines, allowing for more precise and efficient device construction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication methods are used for gated devices, then device functionality is achieved, but processing complexity increases leading to higher costs and reduced throughput
Solution Approach 1:
The fabrication process is divided into distinct sequential steps: forming trenches between walls, filling trenches with dielectric material, performing ion implantation to create doped regions, forming gate dielectric, and selectively etching gate material. This segmentation allows each step to be optimized independently and performed by specialized equipment, reducing overall process complexity and improving throughput.
Solution Approach 2:
The method performs preliminary actions by first forming the trench structure and doped regions before introducing gate materials. The ion implantation step is performed early to establish doped regions that will serve as source/drain regions, which simplifies subsequent processing steps and reduces the need for complex alignment procedures later in the fabrication process.
2Reliability
If conventional fabrication methods are used for gated devices, then device functionality is achieved, but risks of misalignment or other errors increase
Solution Approach 1:
The method performs preliminary actions by first forming the trench structure and doped regions before introducing gate materials. The ion implantation step is performed early to establish doped regions that will serve as source/drain regions, which simplifies subsequent processing steps and reduces the need for complex alignment procedures later in the fabrication process.
Solution Approach 2:
The gate dielectric layer serves as an intermediary between the doped regions and the conductive gate material. This intermediary layer provides a well-defined interface that simplifies alignment requirements, as the gate material can be deposited conformally over the gate dielectric without requiring precise alignment with underlying structures.
3Ease of manufacture
If complex processing is used to form gated devices, then device functionality is achieved, but fabrication costs increase
Solution Approach 1:
The fabrication process is divided into distinct sequential steps: forming trenches between walls, filling trenches with dielectric material, performing ion implantation to create doped regions, forming gate dielectric, and selectively etching gate material. This segmentation allows each step to be optimized independently and performed by specialized equipment, reducing overall process complexity and improving throughput.
Solution Approach 2:
The trench structure and gate dielectric formation provide self-alignment benefits, where the gate material naturally conforms to the trench geometry and gate dielectric profile. This self-service alignment mechanism reduces the need for complex photolithography alignment steps and expensive precision equipment, thereby reducing fabrication costs while maintaining high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the precision and efficiency of gated device fabrication, reducing errors and costs by enabling the formation of well-defined gate structures within the trenches, improving the overall semiconductor fabrication process.
Implementation Method 1
using ion implantation and diffusion to form doped regions
Implementation Method 2
using ion implantation and diffusion to form doped regions
Data Source
AI summary
A method of forming an array of gated devices includes forming trenches between walls that longitudinally extend in rows and project elevationally from a substrate. The walls comprise semiconductor material. Gate dielectric is formed within the trenches laterally over side surfaces of the walls and conductive gate material is formed within the trenches laterally over side surfaces of the gate dielectric. Side surfaces of an elevationally inner portion of the gate material within the trenches are laterally covered with masking material and side surfaces of an elevationally inner portion of the gate material within the trenches are laterally uncovered by the masking material. The elevationally outer portion of the gate material that is laterally uncovered by the masking material is removed while the side surfaces of the elevationally inner portion of the gate material are laterally covered by the masking material to form gate lines within the trenches laterally over elevationally inner portions of the walls.