Gated Device Array Fabrication Using Placeholder Alignment
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Solution Overview
Problem
The complexity of fabricating gated devices in semiconductor fabrication processes increases costs, reduces throughput, and poses risks of misalignment or errors, necessitating the development of new methods for forming arrays of gated devices.
Innovation Solution
The method involves forming arrays of gated devices by creating doped semiconductor regions, depositing and patterning dielectric and metal materials, and forming access and data/sense lines, with specific processing steps to ensure accurate alignment and electrical coupling of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication methods are used for gated devices, then manufacturing capability is maintained, but process complexity increases and throughput decreases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming trenches, depositing placeholder material, patterning walls, and forming metal lines. Each stage独立完成 a specific function, simplifying the overall complex process into manageable segments that can be executed systematically.
Solution Approach 2:
Placeholder material lines are formed in advance within the trenches before the actual metal deposition. This preliminary action establishes the spatial framework and alignment references needed for subsequent processing steps, ensuring precise positioning without requiring complex real-time alignment.
2Reliability
If conventional fabrication methods are used for gated devices, then device functionality is achieved, but misalignment and errors increase
Solution Approach 1:
Placeholder material acts as an intermediary element that facilitates precise alignment between different fabrication stages. These placeholders provide physical references and spatial guides that enable accurate positioning of subsequent structures without requiring complex alignment procedures.
Solution Approach 2:
The placeholder material lines replicate the desired final pattern geometry, creating a template that guides subsequent metal deposition. This copying approach ensures that the final metal structures automatically inherit the precise alignment and spacing defined by the placeholders, reducing alignment errors.
3Ease of manufacture
If conventional fabrication methods are used for gated devices, then device performance is maintained, but manufacturing cost increases
Solution Approach 1:
Placeholder material lines are formed using inexpensive materials and processes that are optimized for simplicity rather than longevity. These placeholders serve their alignment function temporarily during fabrication and are subsequently removed or integrated, eliminating the need for expensive, complex alignment infrastructure.
Solution Approach 2:
The placeholder material lines automatically provide alignment references and spatial guidance for subsequent processing steps without requiring external alignment equipment or complex procedures. The structure itself serves the alignment function, simplifying the manufacturing process and reducing equipment costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces errors, and enhances the efficiency of forming arrays of gated devices, such as transistors and thyristors, by ensuring precise alignment and electrical isolation of components, thereby improving the reliability and cost-effectiveness of semiconductor manufacturing.
Implementation Method 1
The inner region is doped
Implementation Method 2
metal is deposited to be circumferentially surrounding, directly against, and electrically coupled to the sidewalls of the inner region
Data Source
AI summary
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.