Gated Device Array Fabrication via Selective Pillar Etching
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Solution Overview
Problem
The complexity of fabricating gated devices in semiconductor fabrication processes increases costs, reduces throughput, and poses risks of misalignment or errors, particularly in forming arrays of memory cells.
Innovation Solution
A method of forming arrays of gated devices involves creating semiconductor material blocks with doped regions and forming gate lines and pillars using photolithography and etching techniques, allowing for the fabrication of transistors and thyristors with reduced gate-to-pillar capacitive coupling and improved alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used for gated devices, then device functionality is achieved, but manufacturing complexity increases and costs rise
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming semiconductor blocks with doped regions, creating gate lines, and forming pillars through selective removal. This segmentation allows each stage to be optimized independently, reducing overall process complexity while maintaining device functionality
Solution Approach 2:
Semiconductor blocks with pre-formed doped regions are created before gate line formation. This preliminary action simplifies subsequent processing by having the semiconductor structure ready to receive gate lines, reducing the number of alignment steps and overall fabrication complexity
2Productivity
If conventional fabrication processes are used for gated devices, then device functionality is achieved, but throughput is reduced
Solution Approach 1:
Multiple fabrication operations are merged into unified process steps. For example, gate lines are formed laterally proximate to multiple opposing sidewalls in an integrated manner, and pillars are formed through selective removal of semiconductor material across multiple blocks simultaneously. This merging increases throughput by reducing the number of separate processing steps
3Manufacturing precision
If conventional fabrication processes are used for gated devices, then device functionality is achieved, but misalignment and errors increase
Solution Approach 1:
Semiconductor blocks with precisely defined doped regions are formed before gate line deposition. This preliminary structuring provides fixed reference points that simplify alignment during gate line formation, reducing misalignment errors while maintaining process simplicity
Solution Approach 2:
The patent replaces complex mechanical alignment systems with a methodology based on lateral proximity formation. Gate lines are formed laterally proximate to sidewalls through processes that inherently maintain proper spacing, eliminating the need for complex mechanical alignment equipment and procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the efficiency and accuracy of forming gated device arrays, reducing fabrication costs and errors while enabling scalable device design.
Implementation Method 1
forming gate lines laterally proximate to sidewalls of the semiconductor material-comprising blocks
Implementation Method 2
semiconductor material of the blocks is removed laterally between the gate lines to form pairs of pillars
Data Source
AI summary
A method of forming an array of gated devices includes forming a plurality of semiconductor material-comprising blocks individually projecting elevationally from a substrate and spaced from one another along rows and columns. A gate line is formed laterally proximate each of two opposing sidewalls of the blocks along individual rows of the blocks. After forming the gate lines, semiconductor material of the blocks is removed laterally between the gate lines to form pairs of pillars from the individual blocks that individually have one of the gate lines laterally proximate one of two laterally outermost sidewalls of the pair and another of the gate lines laterally proximate the other of the two laterally outermost sidewalls of the pair. Other methods are disclosed.