Gated Flip-Flop Clocking for Lower Power Storage
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Solution Overview
Problem
Flip-flops in integrated circuits consume significant power, particularly in mobile applications, due to their high active power usage, which can dominate the overall power consumption of the circuit.
Innovation Solution
The implementation of a flip-flop device with a gating circuit that generates lower-activity clock signals (clk_nand and clk_nor) from a full-activity input clock signal (CP), reducing the signal transition numbers and thereby lowering the power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional full-activity clock signals are used to control flip-flops, then the flip-flop functionality is maintained, but the power consumption is high
Solution Approach 1:
The patent applies dynamics by making the clock signal activity adaptive rather than static. The gating circuit dynamically adjusts the clock signal transitions based on the master signal state, allowing the system to operate with reduced clock activity when full activity is not needed, thereby reducing power consumption while maintaining functionality when required
Solution Approach 2:
The patent changes the parameter of clock signal activity from full-activity to lower-activity based on operational needs. By modifying the clock signal characteristics (number of transitions) according to the master signal state, the system achieves lower power consumption during storing mode while preserving full functionality during writing mode
2Use of energy by moving object
If the number of clock signal transitions is reduced to lower power consumption, then power consumption decreases, but the ability to maintain flip-flop functionality may be compromised
Solution Approach 1:
The system dynamically adjusts clock signal activity based on the master signal state. During writing mode, the master signal enables full clock activity to ensure proper data capture. During storing mode, the master signal reduces clock activity to minimize power consumption. This dynamic adaptation ensures both productivity and energy efficiency
Solution Approach 2:
The patent implements periodic action through the master signal that periodically enables or disables clock transitions based on the operational phase (writing vs. storing). This periodic control of clock activity allows the system to alternate between high-productivity states and low-power states, achieving both goals over time
Data Source
AI summary
An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.