Gated Tri-State Inverter Phase Interpolator With Miller-Effect Loading
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Solution Overview
Problem
High-power consumption and large footprint issues in phase interpolating (PI) systems due to pull-up/pull-down short-circuit situations, and the use of discrete combinatorial logic circuitry to reduce these issues results in increased size and complexity.
Innovation Solution
A low-power, small footprint PI stage is achieved by using parallel connected tri-state and gated tri-state inverters, with reciprocal operation to avoid short-circuit situations, and a tunable capacitive-loading amplifying stage with a Miller effect configuration to reduce area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If discrete combinatorial logic circuitry is used to reduce pull-up/pull-down short-circuit situations, then power consumption is reduced, but device footprint and complexity increase
Solution Approach 1:
The patent merges the phase interpolation function with tri-state inverter circuits that naturally avoid pull-up/pull-down short-circuit situations. By using inverters with enable inputs controlled by phase interpolation logic, the system achieves both power reduction and compact footprint, as the inverter structures share common transistors and logic paths rather than requiring separate discrete logic blocks for each function.
2Adaptability or versatility
If traditional phase interpolator circuits are used, then phase interpolation function is achieved, but power consumption increases due to pull-up/pull-down short-circuit situations
Solution Approach 1:
The patent converts the potential harmful short-circuit current paths into beneficial power-saving opportunities by using tri-state inverter structures. The enable inputs of the inverters are controlled such that when one inverter is active, the other is in high-impedance state, thereby eliminating the short-circuit condition while maintaining the phase interpolation function through the weighted combination of clock signals.
3Loss of energy
If parallel connected tri-state and gated tri-state inverters are used, then power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent achieves multi-functionality by using the same tri-state inverter structures for both phase interpolation and clock gating functions. The enable inputs serve dual purposes: controlling the active phase interpolator while also gating the clock signals. This universal approach reduces circuit complexity compared to having separate dedicated circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces power consumption and footprint while maintaining efficient phase interpolation, avoiding the drawbacks of high power and large size associated with previous approaches.
Implementation Method 1
a tunable capacitive-loading amplifying stage with a Miller effect configuration to reduce area and power consumption
Data Source
AI summary
A phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage.