Gate-Tunable Negative Differential Resistance for Multi-Valued Logic
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Solution Overview
Problem
Existing negative differential resistance devices have limitations in increasing the number of states in multi-valued logic circuits due to fixed peak and valley current values, which hinders miniaturization and increases power consumption.
Innovation Solution
A negative differential resistance device is configured with a dielectric layer and semiconductor layers, where a third electrode on the dielectric layer's surface can adjust the positions of peak and valley current values by controlling the gate voltage, allowing for multiple peak and valley current values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of multi-valued logic elements is increased to adjust the number and position of peaks, then the peak current values and valley current values can be adjusted, but the area occupied by the circuit increases and miniaturization is hindered
Solution Approach 1:
The patent introduces a third electrode that divides the control function into separate segments. Instead of using multiple multi-valued logic elements, a single element with an additional control electrode is used to independently adjust peak and valley current values through voltage control, thereby reducing the required circuit area while maintaining adjustability.
Solution Approach 2:
The third electrode serves multiple functions: it controls both the peak current value and valley current value of the negative differential resistance element, and can adjust multiple parameters (number of peaks, their positions, and current values) using a single additional component rather than requiring separate control elements for each parameter.
2Adaptability or versatility
If additional resistance elements are added to adjust the current characteristics, then the peak and valley current values can be modified, but the device complexity and surface area increase
Solution Approach 1:
The patent changes the electrical parameter (voltage) applied to the third electrode to control the current characteristics of the negative differential resistance element. By varying the voltage on the third electrode, the peak and valley current values can be adjusted without adding physical resistance elements, thereby reducing device complexity while maintaining full adjustability.
3Adaptability or versatility
If more multi-valued logic elements are used to create multiple peaks, then the number of states increases, but the power consumption increases due to larger connection wire area
Solution Approach 1:
The patent adds a third electrode dimension to the existing two-electrode negative differential resistance element. This additional dimensional control allows the generation of multiple peaks and increased states through voltage control rather than by increasing the number of elements, thereby reducing the connection wire area and associated power consumption while maintaining high state capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the creation of multi-valued logic circuits with increased state values and reduced power consumption by dynamically adjusting the current-voltage characteristics without altering the semiconductor materials.
Implementation Method 1
A negative differential resistance device may configure a multi-valued logic circuit through an N-shaped current characteristic
Implementation Method 2
a first semiconductor layer that includes a first tunneling layer that is on the first surface of the dielectric layer
Data Source
AI summary
A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.


