Gated Ring Oscillator Phase Conversion With Delay-Stable Counters
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Solution Overview
Problem
Phase-to-digital convertors in digital phase locked loops are sensitive to signal transmission delays, which can lead to inaccurate digital representations of phase differences between clock signals.
Innovation Solution
A phase-to-digital convertor that employs a time-to-digital convertor with a stopwatch system, including an oscillator and counters, which generates a digital representation of phase difference by selecting a stable counter value unaffected by signal transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If a time-to-digital converter is used to convert phase difference into digital representation, then the digital PLL can operate with digital components, but the system becomes sensitive to signal transmission delays causing inaccurate phase measurements
Solution Approach 1:
The patent applies preliminary action by pre-establishing multiple fixed time delays (t1, t2, t3, t4) in the delay elements before the measurement process begins. These pre-configured delay paths allow the system to determine phase difference by comparing which pre-established delay path the signal aligns with, thereby eliminating sensitivity to variable signal transmission delays during operation.
Solution Approach 2:
The patent changes the parameter of time delay by using multiple discrete, fixed delay values instead of a continuous or variable delay. By transforming the delay into a set of known, stable parameters (t1 through t4), the system can accurately determine phase difference without being affected by fluctuations in signal transmission delay.
2Adaptability or versatility
If signal transmission delay varies in the system, then the system can adapt to different operating conditions, but the phase-to-digital converter produces inaccurate digital representations
Solution Approach 1:
The system pre-configures multiple fixed delay paths with known time delays before operation. This preliminary setup creates a reference framework that remains stable regardless of varying operating conditions, allowing accurate phase measurement even when signal transmission delay changes.
Solution Approach 2:
The patent employs feedback by comparing the phase detector output with the predetermined delay values and adjusting the determination of phase difference based on this comparison. The feedback mechanism ensures that the digital representation accurately reflects the true phase difference despite variations in signal transmission delay.
Data Source
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AI summary
A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value. A second counter includes an input coupled to an output of another one of the N signal delay elements or the logic gate, wherein the second counter is configured to generate a second digital counter value. The PDC generates the digital output signal based on the low order bits and one of the first and second digital counter values.