Gated Ring Oscillator Phase Converter With Delay-Insensitive Counting
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Solution Overview
Problem
Phase-to-digital convertors in digital phase locked loops are sensitive to signal transmission delays, which can lead to inaccurate digital representations of phase differences between clock signals, affecting the accuracy of digital PLLs.
Innovation Solution
A phase-to-digital convertor employing a stopwatch system with two counters that increment at different points during the oscillator's cycle, allowing the selection of a stable counter value to generate a digital representation of the phase difference, thereby reducing sensitivity to signal transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a time-to-digital converter is used in a digital phase locked loop, then the phase difference between clock signals can be converted into a digital representation, but the accuracy is degraded due to sensitivity to signal transmission delays
Solution Approach 1:
The measurement process is segmented into multiple independent paths: a main measurement path and a delay measurement path. The total measurement time is divided into T1 (main path) and T2 (delay path), allowing the delay component to be separately identified and subtracted from the total measurement, thereby eliminating its harmful effect on accuracy
Solution Approach 2:
The invention implements a feedback mechanism where the measured delay value (proportional to T2) is fed back and subtracted from the total measurement time (T1+T2) to obtain the corrected phase difference. This feedback loop continuously compensates for delay effects, maintaining measurement accuracy despite varying transmission delays
Data Source
AI summary
A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value. A second counter includes an input coupled to an output of another one of the N signal delay elements or the logic gate, wherein the second counter is configured to generate a second digital counter value. The PDC generates the digital output signal based on the low order bits and one of the first and second digital counter values.