Gated Scan Flops for Pre-Bond TSV Probing in 3D ICs
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Solution Overview
Problem
Current methods for pre-bond testing of through-silicon vias (TSVs) in 3D integrated circuits face challenges due to small TSV dimensions and high density, making direct probing unfeasible and existing built-in self-test techniques inefficient, which hinders effective defect detection and increases die-area cost.
Innovation Solution
A modified scan flop, referred to as a gated scan flop, is embedded in the test architecture to enable pre-bond probing of TSVs, combining capacitance, resistance, and leakage tests in a unified scheme using a probe card, allowing for external measurement of resistance and capacitance without large analog components on the die, and reusing post-bond testing features for pre-bond testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If direct probing of TSVs is attempted using conventional probe cards, then measurement capability is provided, but the probe needle contacts multiple TSVs simultaneously due to small TSV pitch, making individual TSV testing unfeasible
Solution Approach 1:
The patent segments the TSV array into groups that can be individually addressed by controlling the switching network. Each TSV or group of TSVs can be isolated and tested separately by activating specific switches in the network, enabling precise measurement despite high density
Solution Approach 2:
The patent introduces a switching network as an intermediary between the probe card and the TSV array. This switching network acts as a mediator that routes probe signals to specific TSVs, enabling individual TSV testing without requiring physically separated probe contacts
2Productivity
If built-in self-test (BIST) techniques are used for pre-bond TSV testing, then testing capability is provided, but observability is limited and measurement types are restricted
Solution Approach 1:
The patent creates a universal test architecture that can perform multiple measurement types (capacitance, resistance, leakage) through a single integrated system combining probe card with switching network, eliminating the limitations of specialized BIST techniques for each measurement type
3Productivity
If conventional BIST approaches are implemented, then testing functionality is achieved, but die-area cost increases due to additional test structures and complex routing
Solution Approach 1:
The patent extracts the complex test structure requirements from the die itself and relocates them to the probe card system. The switching network and control logic are implemented externally, allowing the die to retain minimal test structures while achieving comprehensive testing capability
Solution Approach 2:
The patent creates a universal test architecture that can perform multiple measurement types (capacitance, resistance, leakage) through a single integrated system combining probe card with switching network, eliminating the need for separate BIST circuits for each measurement type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate pre-bond defect screening and localization, allowing defective dies to be discarded before stacking, reducing manufacturing costs and improving yield by minimizing process variation susceptibility and die-area usage.
Implementation Method 1
determining the capacitance of the TSVs through an active driver in the probe head itself
Implementation Method 2
determining the resistance of each TSV by asserting each TSV on to the shorted net
Data Source
AI summary
On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are provided. In accordance with certain embodiments of the invention, a die level wrapper is provided including gated scan flops connected to one end of each TSV. The gated scan flops include a scan flop structure and a gated output. The gated output is controlled by a signal to cause the output of the gated scan flop to either be in a “floated state” or take the value stored in the flip-flop portion of the gated scan flop. The gated output of the gated scan flop can be used to enable resistance and capacitance measurements of pre-bonded TSVs.