Gated Storage Synchronization for Multi-Threaded Processors
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Solution Overview
Problem
Existing multiprocessing systems face inefficiencies in scaling due to long memory latencies and synchronization challenges, particularly when multiple threads from different processors need to access shared resources, and current solutions do not effectively synchronize threads across processors from different manufacturers.
Innovation Solution
A system and method for synchronization that eliminates the need for multiple arbiters and intercommunications between processors by using a single system-level inter-thread communications unit with shared control interfaces and a request storage that can handle access requests from multiple thread contexts within a single clock cycle, allowing for efficient communication and synchronization across multithreaded processors of different architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple arbiters and intercommunications between processors are used for synchronization, then synchronization capability is provided, but device complexity increases
Solution Approach 1:
The patent consolidates multiple per-processor arbiters into a single system-level arbiter that manages access for all processors and thread contexts. Multiple separate intercommunication units are merged into one unified inter-thread communications unit that handles synchronization across the entire multiprocessing system, reducing device complexity while maintaining synchronization capability.
Solution Approach 2:
The single system-level arbiter serves multiple functions by managing access requests from multiple processors and multiple thread contexts within those processors. The unified inter-thread communications unit provides universal synchronization services across heterogeneous processor architectures, eliminating the need for dedicated arbitration and communication infrastructure for each processor.
2Productivity
If each processor has its own request storage for handling access requests, then access request handling capability is provided, but device complexity increases
Solution Approach 1:
The patent consolidates multiple per-processor request storage units into a single shared request storage that receives and manages access requests from all processors and all thread contexts. This unified request storage eliminates redundancy while maintaining the capability to handle multiple concurrent access requests through the single system-level arbiter.
3Reliability
If multiple inter-thread communications units are used for synchronization, then synchronization between threads of different processors is achieved, but device complexity increases
Solution Approach 1:
The patent merges multiple per-processor inter-thread communications units into a single system-level inter-thread communications unit that provides unified synchronization services. This single unit manages inter-thread communication across all processors and handles access requests to shared memory resources, reducing the number of communication units while maintaining comprehensive synchronization capability.
Data Source
AI summary
A gated-storage system including multiple control interfaces, each control interface operatively competed externally to respective multithreaded processors (405A, 405B). The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.