Gated Time-to-Digital Converter in DPLL for Low-Power Phase Sensing
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Solution Overview
Problem
Phase-locked loops (PLLs) in electronic circuits, particularly in portable devices like cellular phones, consume significant power, necessitating a reduction in power consumption without compromising performance.
Innovation Solution
A digital phase-locked loop (DPLL) with a dynamically enabled and disabled time-to-digital converter (TDC) that operates only during short periods to quantify phase information, reducing power consumption by gating the clock signal around the leading edges of the reference signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TDC is continuously enabled to maintain performance, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The TDC is enabled periodically only during short time windows around predicted active edges of the reference signal, rather than continuously. The control unit generates enable signals based on the reference signal to activate the TDC only when phase measurement is needed, achieving both power reduction and maintained measurement precision.
Solution Approach 2:
The control unit predicts when active edges of the reference signal will occur and pre-enables the TDC during these predicted time windows. This preliminary action ensures the TDC is ready to capture phase information exactly when needed, maintaining measurement precision while minimizing active time and power consumption.
2Use of energy by moving object
If the TDC is disabled to reduce power consumption, then power consumption decreases, but measurement precision deteriorates
Solution Approach 1:
Instead of continuously enabling the TDC, the system uses periodic enabling synchronized with the reference signal's active edges. This ensures phase measurement precision is maintained at critical moments while the TDC remains disabled during intervals, achieving power reduction without sacrificing measurement quality.
Solution Approach 2:
The TDC uses the reference signal itself to determine when to enable operation. The control unit generates enable signals based on the reference signal's characteristics, allowing the system to automatically activate the TDC only when phase information is available and needed, eliminating the need for continuous operation.
3Productivity
If the clock signal is continuously active, then productivity is improved, but power consumption increases
Solution Approach 1:
The clock signal to the TDC is gated to be active only during short periodic windows around predicted reference signal edges. This periodic clocking maintains the TDC's ability to process phase information when needed while reducing overall clock signal activity and associated power consumption by approximately 90%.
Solution Approach 2:
The clock signal transitions from a static continuous state to a dynamic gated state, where its activity is modulated based on the reference signal's characteristics. This dynamic approach allows the clock to be active only when phase measurement is required, optimizing both productivity and power consumption.
Data Source
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AI summary
A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.