Gated Varactor Structure for CMOS Tuning Range and Q-Factor
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Solution Overview
Problem
Traditional varactors have limitations such as low tuning range, low Q-factor, high substrate coupling, and incompatibility with CMOS processes, leading to inefficient capacitance variation and phase noise issues in microelectromechanical structures and BiCMOS processes.
Innovation Solution
A four-terminal gated differential varactor structure is developed, utilizing a combination of junction, channel, and oxide capacitors with reverse-biased PN junctions and oxide capacitance, allowing for wider capacitance tuning and improved Q-factor, compatible with CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional varactors are used, then the device can be implemented, but the tuning range is limited and Q-factor is low
Solution Approach 1:
The patent combines multiple capacitor types (junction capacitor, channel capacitor, and oxide capacitor) into a single integrated varactor structure. This merging allows the device to achieve both wide tuning range through the junction capacitor and high Q-factor through the oxide capacitor, resolving the contradiction between adaptability and reliability.
Solution Approach 2:
The varactor employs a composite structure integrating different capacitor technologies with complementary characteristics. The junction capacitor provides voltage-controlled capacitance variation for wide tuning, while the oxide capacitor contributes to high Q-factor, creating a composite device that overcomes the limitations of individual capacitor types.
2Reliability
If traditional varactors are used, then the device can function, but substrate coupling is high causing phase noise
Solution Approach 1:
The patent extracts the harmful substrate coupling effect by introducing a grounded dummy transistor configured as a capacitor that is electrically isolated from the signal path. This extracted structure provides a reference potential that cancels substrate coupling effects, thereby improving phase noise performance without affecting the main varactor operation.
Solution Approach 2:
The dummy transistor acts as an intermediary element between the varactor and the substrate. It mediates the substrate coupling by providing a controlled impedance path to ground, thereby reducing the harmful coupling effects while maintaining the desired electrical characteristics of the varactor.
3Quantity of substance
If NMOS Varactor is used, then oxide capacitance is utilized, but C-V range is limited
Solution Approach 1:
The patent merges the oxide capacitor (from the MOS structure) with the junction capacitor in a unified varactor design. This combination allows the device to benefit from both the voltage-controlled capacitance of the junction capacitor and the stable oxide capacitance, achieving an extended C-V range that overcomes the limitations of using oxide capacitance alone.
4Ease of manufacture
If gated-diode with heavy doped areas is used, then forward PN junction is utilized, but C-V characteristics are limited
Solution Approach 1:
The patent applies local quality by creating regions with different doping concentrations within the varactor structure. The lightly-doped region provides the junction capacitor for wide C-V tuning, while the heavily-doped regions provide stable reference potentials and low impedance paths. This spatial variation in doping quality enables superior C-V characteristics compared to uniform heavy doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced capacitance tuning range, higher Q-factor, reduced substrate coupling noise, and improved phase noise performance, making it suitable for System on Chip (SoC) applications with reduced die area requirements.
Implementation Method 1
a single-ended semiconductor device having a gate node connected to a dual source terminal and to a P+ region, and a drain terminal connected to an N region, which forms a PN junction diode Capacitor-Voltage C-V) characteristic
Implementation Method 2
the device, however, cannot benefit from the oxide capacitance due to the dominated junction capacitance of the forward PN junction
Implementation Method 3
an NMOS Varactor (NMOSVAR) can only benefit from the oxide capacitance and the channel capacitance, which limits the C-V range
Data Source
AI summary
In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.