Gateless Field Transistor ESD Protection for Analog I/O Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ESD protecting circuits with a gate grounded NMOS (GGNMOS) configuration are ineffective in providing adequate protection for analog I/O devices due to high leakage current and inability to reduce breakdown voltage, especially in field transistors without a gate electrode.
Innovation Solution
An ESD protecting circuit and manufacturing method that utilize a field transistor structure without a gate electrode, forming N-type wells and ion implanting to reduce breakdown voltage, incorporating high-concentration impurity regions and a P-type impurity region at the well boundary to control voltage, thereby reducing leakage current and enhancing protection for analog I/O devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a GGNMOS structure is used for ESD protection, then ESD protection capability is improved, but leakage current increases
Solution Approach 1:
The patent changes the fundamental structure from a gated NMOS to a gateless field transistor configuration. By removing the gate electrode and using a simple PN junction structure with optimized doping concentrations, the device achieves ESD protection with significantly reduced leakage current compared to traditional GGNMOS structures.
2Productivity
If the gate insulating layer thickness is reduced for device miniaturization, then device integration is improved, but leakage current increases
Solution Approach 1:
The patent extracts and removes the gate insulating layer and gate electrode from the traditional NMOS structure, creating a gateless field transistor. This eliminates the source of leakage current associated with thin gate insulators while maintaining the ESD protection function through the PN junction mechanism.
3Reliability
If P-type impurity concentration is increased, then ESD trigger voltage is improved, but leakage current increases
Solution Approach 1:
The patent applies different doping concentrations in different regions: high P-type concentration in the substrate for adequate trigger voltage, and optimized N-type concentrations in the field and drain regions. This localized quality differentiation achieves ESD protection while minimizing leakage current through precise spatial control of electrical properties.
4Device complexity
If a field transistor without gate electrode is used, then device simplicity is improved, but breakdown voltage is too high for adequate protection
Solution Approach 1:
The patent modifies the breakdown voltage parameter by optimizing the doping concentrations and junction depths of the PN structure. By carefully controlling the N-type impurity concentration in the field region and the P-type impurity concentration in the substrate, the breakdown voltage is reduced to an appropriate level for ESD protection while maintaining structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and provides adequate ESD protection for analog I/O devices by configuring a field transistor with low breakdown voltage, suitable for sensitive analog circuits.
Implementation Method 1
forming a P-type impurity region below a first high-concentration, N-type impurity region at a boundary between a first well and a second well
Data Source
AI summary
An ESD protecting circuit and a manufacturing method thereof are provided. The ESD protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.