Gateway Synchronization for Accelerator Data Scaling
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Solution Overview
Problem
In scalable computer subsystems acting as work accelerators, ensuring efficient data synchronization between data transfer and processing is challenging, particularly when connecting multiple accelerators, as existing methods struggle to coordinate data exchange phases effectively across the subsystems.
Innovation Solution
A computer system comprising a work accelerator and a gateway that enables synchronized data transfer through pre-compiled code sequences, where a synchronisation instruction indicates a barrier between compute and exchange phases, and a streaming engine executes data transfer instructions triggered by synchronisation acknowledgments, ensuring data is delivered at the correct time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple work accelerators are connected in scalable configurations to increase processing power, then productivity is improved, but data synchronization between data transfer and processing becomes more difficult and latency increases
Solution Approach 1:
The patent applies preliminary action by pre-compiling code sequences that include synchronization instructions indicating barriers between compute and exchange phases. The gateway pre-processes and prepares data transfer instructions before actual data exchange occurs, ensuring that synchronization points are already established and ready to execute, thereby minimizing runtime latency in multi-accelerator configurations.
2Reliability
If barrier synchronization is implemented between compute and exchange phases to ensure data dependencies are met, then reliability is improved, but device complexity increases due to coordinated synchronization across multiple accelerators
Solution Approach 1:
The gateway serves as an intermediary between multiple work accelerators, centralizing the synchronization coordination function. Rather than requiring direct peer-to-peer synchronization between accelerators, the gateway mediates all data exchange operations, receiving synchronization requests from accelerators and coordinating the barrier synchronization across the system, thereby reducing overall device complexity while maintaining reliability.
Solution Approach 2:
The gateway implements multi-functionality by combining data transfer, synchronization coordination, and code sequence management in a single subsystem. This universal approach allows the same gateway infrastructure to handle synchronization for multiple accelerators simultaneously, reducing the need for separate synchronization mechanisms for each accelerator connection and thereby reducing device complexity.
3Productivity
If data transfer is synchronized with processing phases to minimize rest time in accelerators, then productivity is improved, but device complexity increases due to pre-compiled code sequences and streaming engines
Solution Approach 1:
The patent merges the code compilation and execution infrastructure directly into the gateway subsystem. Rather than requiring separate compilation tools and execution environments on each accelerator, the gateway consolidates these functions, pre-compiling code sequences and managing their execution to synchronize data transfer with processing phases. This merging reduces the overall system complexity while maintaining high accelerator utilization efficiency.
Data Source
AI summary
A computer system comprises a work accelerator, a gateway the transfer of data to the accelerator from external storage, the accelerator executes a first compiled code sequence to perform computations on data transferred to the accelerator from the gateway. The first compiled code sequence comprises a synchronisation instruction indicating a barrier between a compute phase in which the compute instructions are executed and an exchange phase, wherein execution of the synchronisation instruction causes an indication of a pre-compiled data exchange synchronisation point to be transferred to the gateway. The gateway comprises a streaming engine storing a second compiled code sequence in the form of a set of data transfer instructions executable by the streaming engine to perform data transfer operations to stream data through the gateway in the exchange phase, wherein the first and second compiled code sequences are generated as a related set at compile time.