Gateway Block for Processor-in-the-Loop Co-Simulation
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Solution Overview
Problem
Existing co-simulation technologies require external processors to be aware of the simulation environment, necessitating wait loops and device driver calls, which complicates testing and increases the risk of code conflicts, especially when transitioning from simulation to deployment.
Innovation Solution
The integration of a target processor into a simulation environment allows it to operate in a processor-in-the-loop (PIL) setting without awareness of the simulation, enabling seamless communication and function calls without the need for wait loops or specific device driver calls, using a gateway block for communication between the block diagram model and external processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external processors use wait loops and device driver calls to communicate with the simulation environment, then the processor can be integrated into the simulation, but the complexity of the processor code increases and the risk of code conflicts increases
Solution Approach 1:
The patent extracts the communication and control logic from the external processor code and relocates it to the simulation environment (host). The processor simply executes its core function while the host handles all coordination, timing, and data transfer through the gateway block, eliminating wait loops and device driver calls from the processor side.
Solution Approach 2:
The gateway block serves as an intermediary between the simulation environment and the external processor. It manages the communication channel, handles data transfer, and coordinates function calls, allowing the processor to operate independently without direct knowledge of the simulation environment.
2Ease of operation
If the processor is made aware of the simulation environment through wait loops and device drivers, then communication can be established, but the ease of transitioning from simulation to deployment is reduced
Solution Approach 1:
The patent extracts all simulation-specific awareness code (wait loops, device drivers, handshaking mechanisms) from the processor and relocates it to the host simulation environment. The processor code remains clean and deployment-ready, while the host handles all simulation-specific coordination.
Solution Approach 2:
The gateway block creates a virtual copy of the communication interface that presents a consistent abstraction layer. This allows the processor to interact with the simulation environment through a standardized interface that behaves identically in both simulation and deployed modes, eliminating code conflicts.
3Reliability
If traditional co-simulation technology is used with peer-to-peer handshaking, then the processor can be integrated, but the time required for testing and evaluation increases
Solution Approach 1:
The patent implements preliminary action by having the host simulation environment proactively invoke processor functions through the gateway block at appropriate simulation time steps. This eliminates the need for the processor to continuously wait and handshake, as the host initiates communication based on the simulation timeline, significantly reducing testing time.
Solution Approach 2:
The gateway block implements feedback mechanisms where the host monitors simulation state and automatically triggers processor function calls when needed. This closed-loop approach eliminates manual handshaking and wait loops, allowing rapid iteration and evaluation of processor functionality within the simulation context.
Data Source
AI summary
The present invention relates to integration of an external processor capable of execution of one or more functions into a block diagram model environment such that the block diagram model environment can make function calls directly into the external processor without the need for traditional wait loops or handshaking means. Furthermore the results of the function that was called in the external processor can be passed to the block diagram model environment from the external processor.