Onboard Computer Gateway Interrupt Management for Real-Time Vehicle Control
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Solution Overview
Problem
Current onboard computer systems in vehicles face real-time processing challenges due to the lengthy monopolization of CPU resources by the gateway function, which can negatively affect safety-critical operations such as vehicle stability and emergency braking.
Innovation Solution
A method and computer configuration that manage frames by receiving data messages from one bus, storing them in a buffer, triggering an interrupt for processing, deactivating the interrupt after a determined duration to resume operational program execution, and re-triggering it after a timeout to continue processing messages, thereby smoothing the load on the computer and maintaining real-time performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gateway function monopolizes CPU resources to process all received frames, then the gateway function can be completed, but the real-time performance of operational functions deteriorates
Solution Approach 1:
The patent implements periodic interrupt activation where the interrupt is triggered at regular intervals (e.g., every 10ms) rather than continuously. The frame manager checks whether to activate the interrupt based on accumulated frame counts or time intervals, allowing operational functions to execute without interruption during non-interrupt periods while still processing gateway frames periodically.
Solution Approach 2:
The patent dynamically adjusts interrupt activation based on real-time conditions. The frame manager evaluates the current state (number of buffered frames, CPU load, operational function priorities) to determine whether to activate or deactivate the interrupt at any given moment, making the system adaptive rather than static.
2Productivity
If the interrupt remains active to process all frames, then the gateway function is thorough, but the operational program execution is continuously interrupted
Solution Approach 1:
The patent processes only a subset of buffered frames during each interrupt activation rather than all frames. The frame manager selectively processes frames based on priority, operational function requirements, or buffer depth thresholds, leaving some frames to be processed in subsequent interrupt cycles, thus balancing gateway throughput with operational function continuity.
3Reliability
If dedicated gateway processors are used, then the gateway function is specialized, but the cost increases
Solution Approach 1:
The patent makes the onboard computer universal by enabling it to perform both operational functions and gateway functions using the same CPU and frame manager. The interrupt mechanism and buffer management system allow the single computer to dynamically switch between or concurrently handle different functional roles, eliminating the need for separate dedicated gateway processors.
Data Source
AI summary
A method for managing frames in a computer providing an operational function and a gateway function between two communication buses in order to transmit messages from a transmitter to a receiver, including: receiving messages from a transmitter via the first bus; storing the received messages; triggering an interrupt of the execution of an operational program causing the processing of the stored messages for transmission to the receiver via the second bus; deactivating the interrupt in order to continue the execution of the functional program, after the expiration of a duration and at the end of the processing of a message currently being processed during the expiration; and, triggering a new interrupt at the end of a timeout of a duration of the execution of the operational program causing the processing of messages stored for transmission to the receiver via the second bus to continue.