Gather and Scatter Data Transfer for Irregular Memory Access

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Solution Overview

Problem

SIMD architectures face inefficiencies in applications with irregular memory access patterns, such as data tables requiring frequent updates, due to the overhead of rearranging data elements stored in non-contiguous memory locations, which limits the utilization of SIMD hardware.

Innovation Solution

Implementing gather and scatter operations that decode a single instruction for data transfer between storage locations, handle exceptions by delivering pending interrupts to an exception handler before delivering the exception, and using a finite state machine for address generation and microcode for loads/stores to optimize data packing and unpacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data elements are stored in non-contiguous memory locations to support irregular memory access patterns, then application flexibility is improved, but SIMD hardware utilization deteriorates due to rearrangement overhead

Engineering Contradiction:
Improveapplication flexibilityVSAvoidSIMD hardware utilization
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the data transfer process into distinct gather and scatter operations. Gather operations collect data elements from non-contiguous memory locations into contiguous SIMD registers, while scatter operations distribute data from SIMD registers back to non-contiguous memory locations. This segmentation allows SIMD hardware to operate on contiguous data while supporting irregular memory access patterns, resolving the contradiction between application flexibility and SIMD utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces SIMD registers as an intermediary between non-contiguous memory locations and SIMD processing units. Data elements are first gathered into contiguous SIMD registers from scattered memory locations, processed by SIMD hardware, then scattered back to the original non-contiguous locations. This intermediary approach enables SIMD hardware to work with contiguous data while maintaining support for irregular memory access patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If data rearrangement is performed to fully utilize SIMD hardware, then processing speed is improved, but overhead increases substantially

Engineering Contradiction:
Improveprocessing speedVSAvoidoverhead
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts the data rearrangement overhead from the critical SIMD processing path by implementing dedicated gather and scatter operations. These operations perform the necessary data movement and rearrangement separately from the SIMD computation, allowing SIMD hardware to operate at full speed on contiguous data while the rearrangement overhead is handled by specialized instructions that do not bottleneck the processing pipeline.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If vector widths are increased to improve SIMD performance, then parallel processing capability is improved, but difficulty in utilizing hardware increases due to rearrangement overhead

Engineering Contradiction:
Improveparallel processing capabilityVSAvoiddifficulty in utilizing hardware
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the complex data transfer and processing operations into distinct gather, process, and scatter phases. This segmentation becomes increasingly beneficial as vector widths increase, because the gather and scatter operations can be optimized independently for wide vectors, while the processing phase operates on fully contiguous data without rearrangement overhead. The separation of concerns makes it easier to utilize wide SIMD hardware effectively.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10175990B2Gathering and scattering multiple data elements
Publication Date: 2019.01.08 INTEL CORP
  • US10175990B2 patent drawing
  • US10175990B2 patent drawing
  • US10175990B2 patent drawing

AI summary

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.