Gaussian-Blur Sample Rate Conversion for Asynchronous Data Recovery
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Solution Overview
Problem
Existing methods for recovering asynchronous data into a fixed clock domain often require phase-locked loops (PLLs) with analog components like phase detectors and voltage-controlled oscillators (VCOs, which suffer from jitter and false lock issues, necessitating complex design considerations and additional processing to synchronize with a system clock.
Innovation Solution
A circuit using a modified quadrature resolver replaces the PLL, employing frequency dividers, oscillators, multipliers, and low-pass filters to recreate the dominant frequency of the input data stream without analog components, allowing data recovery on a single clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) with analog components is used to recover asynchronous data, then data recovery is achieved, but jitter and false lock issues occur degrading the recovered data quality
Solution Approach 1:
The patent replaces the analog PLL system with a fully digital implementation using a digital signal processor. The digital signal processor implements a numerically controlled oscillator and digital phase detector, eliminating analog components that cause jitter and false lock. The digital architecture processes the asynchronous data stream through digital filtering and frequency synthesis to recover data at the dominant frequency without the harmful effects of analog circuitry.
2Reliability
If a PLL is used to recover asynchronous data at a different frequency than the system clock, then data recovery is achieved, but additional processing is required to synchronize with the system clock
Solution Approach 1:
The digital signal processor is configured to perform multiple functions: it recovers asynchronous data at the dominant frequency and simultaneously synchronizes the recovered data to the system clock domain. The digital architecture allows flexible frequency translation and phase alignment without requiring separate synchronization circuits, reducing overall system complexity while maintaining data recovery capability.
3Reliability
If analog components such as phase detectors and VCOs are used in data recovery, then frequency locking is achieved, but the design becomes complicated with multiple design considerations
Solution Approach 1:
The patent substitutes all analog components (phase detectors, VCOs, filters) with digital equivalents implemented in a digital signal processor. The numerically controlled oscillator replaces the analog VCO, digital phase detection algorithms replace analog phase detectors, and digital filtering replaces analog filters. This consolidation into a single digital processing unit dramatically reduces design complexity while maintaining frequency locking functionality through software-configurable parameters.
Data Source
AI summary
Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.