Gaussian-Pulse Digital Logic for Low-Emission Clocked Circuits
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Solution Overview
Problem
Digital circuits generate broadband spectral content due to square waveforms, leading to unwanted EMI/RFI emissions that degrade sensor and analog component performance, making it challenging to comply with EMI/RFI regulations and potentially pose health hazards.
Innovation Solution
Implementing spectrally efficient digital logic using Gaussian-shaped pulses that reduce spectral content, integrating product signals over a clock period to determine logic states, and outputting pulses over a second half of the clock period, thereby reducing EMI/RFI emissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If square waveforms are used in digital circuits, then digital logic functionality is achieved, but broadband spectral content and EMI/RFI emissions are generated
Solution Approach 1:
The patent changes the waveform parameter from square wave to spectrally-efficient pulse shape (such as Gaussian pulses). This parameter change maintains the digital logic functionality while reducing the broadband spectral content and EMI/RFI emissions generated by sharp transitions in square waves.
Solution Approach 2:
The patent employs periodic clocked operation where integration occurs during a first portion of the clock period and output is provided during a second portion. This periodic action structure allows the circuit to maintain reliable digital logic functionality while controlling spectral emissions through timed operation phases.
2Object-generated harmful factors
If spectrally-efficient pulses are used, then EMI/RFI emissions are reduced, but circuit complexity increases due to integration and pulse generation requirements
Solution Approach 1:
The patent combines multiple functions into integrated circuit blocks: the multiplier circuit integrates signal multiplication and pulse generation, the integrator circuit combines integration and logic state determination, and the limit circuit merges threshold detection and output control. This merging reduces overall system complexity despite the sophisticated waveform processing required.
Solution Approach 2:
The spectrally-efficient digital logic circuit performs multiple functions: it generates spectrally-efficient pulses, integrates product signals over clock periods, determines logic states, and provides controlled output signals. This multi-functionality is achieved through a unified circuit architecture that reduces the need for separate dedicated circuits for each function.
3Measurement precision
If product signal is integrated over first-half of clock period, then logic state determination is achieved, but output is delayed to second-half of clock period
Solution Approach 1:
The circuit performs preliminary integration of the product signal during the first-half of the clock period to determine the logic state before the output phase. This preliminary action allows accurate logic state determination to be completed in advance, with the result ready for immediate output when the second-half phase begins, minimizing effective delay.
Solution Approach 2:
The circuit operates in periodic phases: integration during the first portion of the clock period and output during the second portion. This periodic action structure accepts and manages the inherent timing delay as part of the operational cycle, ensuring that logic state determination is completed with precision before output occurs.
Data Source
AI summary
Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for combinatorial or sequential logic elements and circuits. A SEDL circuit includes a multiplier circuit configured to receive a clock signal and provide a product of the input signal and a clock signal, an integrator circuit to integrate the product signal over a first portion of a clock period to determine the logic state of the input signal, a limit circuit configured to apply limits to a state result provided to the integrator circuit, and a pulse generator configured to receive the logic state from the limit circuit and provide and output signal having a Gaussian-shaped output pulse that represents that logic value corresponding to the logic value of the input signal.