Generalized Concatenated Codes for High-Rate Flash Memory ECC
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Solution Overview
Problem
Existing error correction coding methods for non-volatile flash memories, such as those based on Generalized Concatenated Codes, face limitations in achieving high code rates due to constraints in spare memory area and decoding complexity, particularly in flash memories with limited redundancy storage.
Innovation Solution
The method employs generalized concatenated coding constructed from L inner nested binary extended Bose-Chaudhuri-Hocquenghem (BCH) codes and L outer Reed-Solomon codes, where the lowest nesting level uses a single parity-check (SPC) code, enabling high-rate error correction encoding and decoding with increased efficiency and reduced redundancy overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional GC codes with nested BCH codes are used for error correction in flash memories, then error correction capability is improved, but code rate is limited to below 0.9 due to spare memory area constraints
Solution Approach 1:
The patent changes the parameter of the inner code at the lowest nesting level from a full BCH code to a Single Parity Check (SPC) code. This parameter change reduces the redundancy overhead significantly, enabling code rates above 0.9 while maintaining acceptable error correction capability through the outer Reed-Solomon codes and the nested structure of the remaining BCH codes at higher levels.
Solution Approach 2:
The patent segments the error correction function across multiple nesting levels, with the lowest level (level 0) handling simple parity checks and higher levels (1 to L-1) handling more complex BCH error correction. This segmentation allows the system to achieve high code rates at the first level while maintaining robust error correction through the hierarchical structure, resolving the contradiction between code rate and error correction capability.
2Reliability
If more redundancy is allocated for ECC to improve error correction, then reliability is improved, but spare memory area consumption increases
Solution Approach 1:
By changing the inner code parameter at level 0 from BCH to SPC, the patent dramatically reduces the redundancy bits required for error correction. The SPC code requires only 1 parity bit per data block, whereas a BCH code would require many more bits. This parameter change enables high reliability with minimal spare memory area consumption, achieving code rates above 0.9.
Solution Approach 2:
The patent applies different error correction strategies at different nesting levels: simple SPC at level 0 for efficient space utilization, and more powerful BCH codes at higher levels where needed. This local differentiation of error correction quality allows the system to optimize the balance between reliability and memory area usage, providing high reliability where necessary while minimizing overall redundancy overhead.
3Reliability
If complex BCH codes are used for error correction, then error correction capability is improved, but decoding complexity increases
Solution Approach 1:
The patent segments the decoding complexity across nesting levels, with the simplest SPC decoding at level 0 and progressively more complex BCH decoding at higher levels. This segmentation allows the majority of data blocks to undergo simple and fast SPC decoding, while only a smaller subset requires the more complex BCH decoding, thereby reducing the average decoding complexity while maintaining high error correction capability.
Solution Approach 2:
Instead of applying complex BCH decoding to all data blocks, the patent uses partial action by applying SPC decoding (a simpler code) to the lowest nesting level for all blocks, and reserves the more complex BCH decoding capability for higher nesting levels only when needed. This partial application of complex decoding reduces overall computational complexity while maintaining sufficient error correction capability through the hierarchical structure.
Data Source
AI summary
Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.