GCIB Insulating Layer Formation for Pillar Exposure
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Solution Overview
Problem
The existing semiconductor device manufacturing process faces challenges in detecting the optimal timing for exposing the upper surface of a pillar from an insulating layer, requiring the combination of multiple techniques like CMP, RIE, and IBE, and involves complex verification processes that increase manufacturing time and cost.
Innovation Solution
The method involves forming a pillar on a base layer, covering it with an insulating layer using the GCIB method where the lowermost portion of the upper surface of the insulating layer is lower than the pillar's surface, and using CMP with torque current monitoring to determine the end point of polishing, thereby simplifying the process and reducing the number of manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMP, RIE, and IBE are combined to expose the pillar surface, then the pillar can be exposed from the insulating layer, but the manufacturing process becomes complex and time-consuming
Solution Approach 1:
The patent merges the insulating layer formation and pillar exposure functions into a single GCIB etching process. The GCIB method simultaneously forms the insulating layer and exposes the pillar head by controlling the etching depth to reach the pillar surface, eliminating the need for separate CMP, RIE, and IBE processes.
Solution Approach 2:
The patent implements feedback control by monitoring the etching process in real-time using a sensor that detects when the pillar surface is exposed. This feedback mechanism allows automatic termination of the etching process at the precise moment the pillar head emerges, ensuring reliable exposure without requiring complex multi-step processes or sample verification.
2Manufacturing precision
If multiple etching techniques are used to expose the pillar, then the pillar surface can be revealed, but the manufacturing time increases
Solution Approach 1:
The patent performs preliminary action by pre-forming the insulating layer with a thickness that is intentionally made smaller than the pillar height before the etching process. This preliminary configuration ensures that the subsequent GCIB etching process will naturally expose the pillar surface when it removes the insulating layer, eliminating the need for time-consuming sample verification to determine optimal etching parameters.
Solution Approach 2:
The patent uses real-time feedback monitoring during the GCIB etching process to detect when the pillar surface is exposed. This feedback control allows the process to automatically terminate at the precise exposure point, achieving high manufacturing precision while significantly reducing the time required compared to conventional methods that require multiple steps and sample verification.
3Manufacturing precision
If the insulating layer thickness is optimized by sample verification, then the pillar exposure can be controlled, but the manufacturing cost increases
Solution Approach 1:
The patent replaces expensive sample verification processes with a real-time feedback monitoring system during production. The sensor detects the exact moment when the pillar surface is exposed during the GCIB etching process, allowing precise control of pillar exposure without requiring multiple sample iterations. This feedback mechanism eliminates the need for costly sample verification while maintaining high manufacturing precision.
Solution Approach 2:
The patent implements self-service by designing the GCIB etching process to automatically control the insulating layer removal and pillar exposure based on real-time detection. The system self-regulates the etching depth by monitoring the exposure condition, eliminating the need for external sample verification and manual adjustment, thereby reducing manufacturing costs while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable exposure of the pillar surface without the need for sample verification, shortening the manufacturing time and reducing costs by integrating the insulating layer as both a protective and interlayer dielectric layer, while preventing damage to the pillar during processing.
Implementation Method 1
forming an insulating layer on the base layer to cover the pillar by using GCIB method
Implementation Method 2
polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method
Data Source
AI summary
According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.