Graph Convolutional Network for Chip Design Optimization
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Solution Overview
Problem
The increasing complexity of integrated circuit (IC) design makes it prohibitively expensive in terms of time and computing resources to evaluate design changes, as conventional electronic design automation (EDA) tools rely on coarse-level simulations that struggle to accurately predict quality-of-results (QoR) metrics such as power, performance, and area.
Innovation Solution
A reinforcement learning (RL) based chip design optimization system utilizing trained graph convolutional networks (GCN) to predict end-to-end QoR metrics from register transfer level (RTL) design parameters, enabling faster and more accurate design decisions by automating design optimizations within suitable timeframes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional EDA tools are used for full physical design runs to evaluate design changes, then measurement precision of QoR metrics is improved, but loss of time and computing resources increases
Solution Approach 1:
The patent creates a trained GCN model that serves as a virtual copy of the full physical design process. This model is trained on data from actual EDA tool runs and then used to predict QoR metrics without executing the complete physical design flow again, enabling fast evaluation while maintaining reasonable accuracy
Solution Approach 2:
The patent performs full physical design runs in advance to collect training data, then uses this pre-computed information to quickly evaluate design changes. The GCN model is trained beforehand on comprehensive design data, allowing rapid prediction without repeating the full design process
2Manufacturing precision
If conventional EDA tools perform full physical design runs to evaluate design quality, then manufacturing precision of design evaluation is improved, but device complexity requirements increase
Solution Approach 1:
The trained GCN model acts as a simplified copy that captures the essential behavior of complex EDA tools. Once trained, the model provides accurate predictions without requiring the full computational infrastructure of conventional EDA tools, reducing device complexity for evaluation tasks
Solution Approach 2:
The patent transforms the evaluation process from requiring full physical design parameters and computational resources to using a trained neural network model with fixed weights. This parameter transformation enables accurate evaluation with reduced computational complexity
3Productivity
If reinforcement learning with trained GCN is used for design optimization, then productivity of design exploration is improved, but device complexity of the optimization system increases
Solution Approach 1:
The patent uses a trained GCN model that encapsulates complex optimization knowledge in a compact neural network structure. This model copy enables rapid design space exploration without requiring complex real-time simulation infrastructure
Solution Approach 2:
The GCN model is trained in advance on comprehensive design data and optimization outcomes. This preliminary training phase captures complex design relationships, enabling the system to quickly evaluate and optimize designs without repeating complex analysis during the optimization process
Data Source
AI summary
Reinforcement learning (RL) based chip design optimization using trained graph convolutional networks (GCN) may include generating an elaborated circuit design based on a high-level circuit design and permuton values for permutons of the high-level circuit design, inferring metrics of the elaborated circuit design with a machine-learning (ML) engine, evaluating the inferred metrics and the permuton values of the elaborated circuit design and revising the permuton values based the evaluation to optimize the inferred metrics, using a RL engine, and revising the elaborated circuit design based on the revised permuton values. An apparatus may include a ML engine that infers metrics of an elaborated circuit design, and a RL engine that determines a correlation between the inferred metrics and permuton values of the elaborated circuit design and revises the permuton values based on the inferred metrics and the correlation to optimize the inferred metrics with respect to optimization criterion.