Graph Convolutional Network for Netlist Testability Analysis

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Deep learning techniques face challenges in applying to Computer Aided Design (CAD) and Electronic Design Automation (EDA) problems, particularly in representing netlists as directed acyclic graphs, which requires complex preprocessing and loses data structure, making it difficult to train deep neural networks effectively.

Innovation Solution

A pre-processor is developed to levelize netlists, compute controllability and observability, and formulate them as collections of fan-in and fan-out nodes, followed by the application of a graph convolutional network (GCN) to analyze and improve testability by inserting test points, leveraging SCOAP algorithm and node embeddings to enhance training and inference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If netlists are represented as directed acyclic graphs for deep learning processing, then the circuit connectivity can be analyzed, but data structure is lost and complex preprocessing is required

Engineering Contradiction:
Improvetestability analysis accuracyVSAvoidpreprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary preprocessing module that transforms netlists into a suitable format for deep learning without losing essential structural information. This intermediary representation serves as a bridge between the original netlist format and the deep learning model requirements, maintaining data integrity while enabling effective processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary actions by performing controllability and observability analysis before feeding data into the deep learning model. This preprocessing step prepares the data in advance, computing key metrics that guide the subsequent test point insertion decisions, thereby reducing the complexity during the main inference phase.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If conventional software tools are used for CAD and EDA problems, then general purpose solutions are available, but company-specific data and internal knowledge cannot be leveraged

Engineering Contradiction:
Improvecompany-specific data utilizationVSAvoidtestability analysis accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the parameters of the analysis system by training deep learning models on company-specific historical data and internal knowledge. This allows the system to adapt to proprietary design patterns, methodologies, and data characteristics, improving both adaptability to company-specific requirements and the reliability of testability predictions through learned patterns.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If deep learning models are trained with preprocessed netlist data, then faster results can be obtained, but data and structure may be lost during preprocessing

Engineering Contradiction:
Improveanalysis speedVSAvoidcircuit data loss
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent applies local quality by selectively preserving critical local structures and relationships in the netlist data during preprocessing. Instead of uniform processing, the method maintains essential local connectivity information and structural characteristics where they are most needed for testability analysis, while still enabling fast deep learning processing.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10657306B1Deep learning testability analysis with graph convolutional networks
Publication Date: 2020.05.19 NVIDIA CORP
  • US10657306B1 patent drawing
  • US10657306B1 patent drawing
  • US10657306B1 patent drawing

AI summary

Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.