GDDR Decision Feedback Equalization Training Scheme
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Solution Overview
Problem
High-speed memory systems face challenges in quickly training Decision Feedback Equalization (DFE) coefficients at startup to minimize downtime, while maintaining optimal signal detection and reducing hardware redundancy, especially in single-ended signaling applications like GDDR and DDR memory systems.
Innovation Solution
A hardware-based receiver eye scan approach is implemented to determine optimal DFE coefficients by training at startup using a reference bit-stream receiver and error receiver, which reuses hardware for normal operation, avoiding continuous coefficient adjustments and minimizing errors, thus setting a stable reference voltage for accurate data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DFE coefficients are continuously trained with higher step size, then adaptation speed is improved, but measurement precision deteriorates due to inaccurate transition identification
Solution Approach 1:
The patent performs preliminary DFE coefficient training at startup before normal operation begins. By completing the training process in advance using a controlled training mode, the system establishes accurate reference voltages without the need for continuous adjustments during data transmission, thereby avoiding the precision problems associated with continuous adaptation.
Solution Approach 2:
The patent segments the DFE training process into distinct phases: a training mode phase where coefficients are established using known training patterns, and a normal operation phase where the trained coefficients are used without further adjustment. This segmentation allows the system to achieve both fast initial adaptation and high measurement precision during data reception.
2Device complexity
If DFE training is performed at startup only, then hardware complexity is reduced, but productivity deteriorates due to extended downtime
Solution Approach 1:
The patent implements continuous monitoring of signal quality metrics during normal operation to detect when retraining may be beneficial. This allows the system to maintain productivity by only interrupting operation when necessary, rather than requiring continuous training or accepting degraded performance.
Solution Approach 2:
The patent employs periodic retraining cycles where the system briefly interrupts data reception to retrain DFE coefficients based on accumulated signal characteristics. This periodic approach balances the need for accurate coefficient training with the requirement to maintain high productivity during data transmission.
3Measurement precision
If separate training hardware is added, then measurement precision is improved, but device complexity increases due to hardware redundancy
Solution Approach 1:
The patent designs the DFE training circuitry to serve multiple functions: it operates as a full-featured training system during the training phase and then transitions to being part of the normal reception pipeline during data operation. The same hardware components are reused in different modes, eliminating the need for separate dedicated training hardware and reducing overall device complexity.
Solution Approach 2:
The patent merges the training function with the normal reception function by using the same receiver and processing pipeline for both purposes. During training, the system processes known training patterns through the DFE to establish coefficients; during normal operation, the same pipeline processes data using the trained coefficients without requiring separate hardware paths.
Data Source
AI summary
The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.