GDDR PHY Self-Clocking for Accurate Read Data Sampling

The patent introduces an intermediary clock signal generation mechanism where the PHY circuit generates its own clock signals (first clock signal, second clock signal, third clock signal) to sample incoming serial data. This intermediary clock system acts as a mediator between the absent DRAM clock signal and the data sampling requirement, enabling the PHY circuit to autonomously synchronize and sample data during read operations without direct clock input from the GDDR DRAM.

The PHY circuit performs self-service by generating its own gate signals and clock signals internally rather than relying on external clock signals from the GDDR DRAM. The circuit uses its own resources (logic units, delay elements) to create the necessary timing signals for data sampling, making the system self-sufficient during read operations when the DRAM does not provide clock signals.

The patent segments the clock signal generation into distinct functional units: a first logic unit generates the first clock signal for initial sampling, a second logic unit generates the second clock signal for intermediate processing, and a third logic unit generates the third clock signal for final deserialization. This segmentation allows each unit to be optimized independently and simplifies the overall control logic by dividing the complex timing requirements into manageable, specialized components.

The system dynamically selects and switches between different clock signals based on the operational phase. During different stages of data reception and processing, the PHY circuit activates appropriate clock signals (first, second, or third) as needed. This dynamic approach allows the circuit to maintain high data recovery accuracy by using the most appropriate clock signal for each specific operation, while avoiding the constant overhead of all clock generation circuits operating simultaneously.