GDDR4 Memory Write Training for Bit Positioning Accuracy
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Solution Overview
Problem
The GDDR4 SGRAM specification's tolerance in write data strobe signal synchronization at higher operating frequencies leads to bit positioning uncertainty, making it difficult to distinguish between early or late phases, which affects data transfer accuracy in graphics memory systems.
Innovation Solution
A memory system incorporating a write training block, output pointer counter, and multiplexer to synchronize the write data strobe signal with the external clock, using a FIFO to manage data alignment and a multiplexer to adjust the output pointer based on read data, ensuring accurate bit positioning during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the GDDR4 SGRAM specification's tolerance range of -500 to +500 ps is used for TDQSS at higher operating frequencies, then the memory can operate at higher frequencies, but bit positioning uncertainty increases making it difficult to distinguish between early and late phases
Solution Approach 1:
The patent performs write training operations before normal write operations to determine the actual bit position of write data. By preliminarily training and calibrating the system, the memory can compensate for timing variations and accurately identify bit positions even at higher frequencies where timing tolerance is relaxed.
Solution Approach 2:
The patent uses feedback from read operations to determine the actual bit position of previously written data. The system reads back write data, compares expected versus actual positions, and uses this feedback information to adjust and correct bit positioning for subsequent operations, thereby maintaining accuracy despite relaxed timing tolerances.
2Adaptability or versatility
If the write latency is made programmable from one to seven clock cycles, then the memory can adapt to different performance requirements, but the complexity of timing synchronization increases
Solution Approach 1:
The patent performs write training and bit position determination before actual write operations. This preliminary calibration establishes the correct timing relationships and bit positions in advance, simplifying the timing synchronization for subsequent operations with different write latency settings.
Solution Approach 2:
The patent makes the write latency programmable and adaptive, allowing the system to dynamically adjust the number of clock cycles between write command and data registration. This dynamic configuration enables optimization for different performance requirements while the write training mechanism handles the complexity of timing synchronization.
Data Source
AI summary
A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.