GdGaO/Ga2O3 Dielectric Stack for III-V MOSFET
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Solution Overview
Problem
There is a need for an improved method and apparatus for III-V compound semiconductor heterostructure MOSFET process flow that utilizes a GdGaO/Ga2O3 dielectric stack as a gate oxide, particularly requiring an implant-free enhancement mode structure and process, while ensuring minimal interface damage and high performance.
Innovation Solution
The method involves using a GdGaO/Ga2O3 dielectric stack as a gate oxide, employing a protective AlN layer for interface protection, forming ohmic contacts that overlap the gate oxide to prevent depletion, and utilizing water vapor annealing to reduce interface state density, along with high workfunction gate metal for enhancement mode operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a GdGaO/Ga2O3 dielectric stack is used as gate oxide, then device performance and thermal stability are improved, but process complexity increases
Solution Approach 1:
The gate oxide is segmented into a stacked structure of GdGaO and Ga2O3 layers, where each layer performs a specific function: GdGaO provides high dielectric constant for strong gate control, while Ga2O3 provides thermal stability and interface quality. This segmentation allows optimization of different properties in separate layers rather than requiring a single complex material.
Solution Approach 2:
The patent employs a composite dielectric stack combining GdGaO and Ga2O3 materials. This composite structure leverages the advantageous properties of each material: GdGaO's high-k characteristic for improved device performance and Ga2O3's thermal stability for process compatibility, thereby achieving both performance improvement and process feasibility.
2Ease of manufacture
If an implant-free enhancement mode structure is used, then manufacturing simplicity is improved, but achieving adequate threshold voltage control becomes difficult
Solution Approach 1:
The patent achieves threshold voltage control in the implant-free structure by adjusting material parameters, specifically the dielectric constant of the gate oxide stack and the thickness ratios of GdGaO and Ga2O3 layers. By changing these parameters, adequate voltage control is achieved without requiring ion implantation processes.
Solution Approach 2:
The Ga2O3 layer acts as an intermediary between the GdGaO high-k dielectric and the semiconductor interface, providing a transition zone that ensures good interface quality and electrical characteristics. This intermediary layer enables adequate threshold voltage control while maintaining the simplicity of the implant-free manufacturing approach.
3Reliability
If AlN protective layer is used for interface protection, then interface state density is reduced, but additional processing steps are required
Solution Approach 1:
The AlN protective layer is deposited preliminarily on the semiconductor surface before the gate oxide formation. This preliminary action passivates the interface and reduces interface state density before subsequent processing steps, ensuring a clean starting point for the dielectric stack formation and improving overall interface quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher performance, smaller die size, improved linearity, lower noise, and increased integration levels for RF applications, combining the advantages of MOS and III-V semiconductor technologies, with enhanced thermal stability and reduced interface defects.
Implementation Method 1
utilizing water vapor annealing to reduce interface state density
Implementation Method 2
using a GdGaO/Ga2O3 dielectric stack as a gate oxide
Data Source
AI summary
A method of forming a compound semiconductor device comprises forming a gate insulator layer overlying a compound semiconductor substrate, defining an active device region within the compound semiconductor substrate, forming ohmic contacts to the compound semiconductor substrate proximate opposite sides of the active device region, and forming a gate metal contact electrode on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts having portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure an avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.