GDMA Loopback Transfers in Media Controller Architecture
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Solution Overview
Problem
NAND flash memory devices face limitations in random access and endurance due to their I/O interface, which does not support full address and data bus capability, requiring additional controller logic for mapping logical to physical addresses and frequent block erasures, leading to reduced device lifespan and inefficiencies in data transfer operations.
Innovation Solution
A media controller with a generic direct memory access (GDMA) system that links transmit and receive data paths, utilizing buffers and status entries to process and synchronize data, enabling efficient data transfer and management of movable data across the memory storage system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NAND flash memory uses block-based erase operations, then write endurance is improved, but data transfer efficiency deteriorates due to frequent erasures
Solution Approach 1:
The patent introduces a buffer memory as an intermediary between the host and NAND flash memory. The buffer temporarily stores data during read and write operations, allowing the system to perform sequential buffer operations instead of direct random access to flash memory blocks. This mediator enables efficient data transfer while the flash memory maintains its block-based erase structure for endurance protection.
2Device complexity
If NAND flash memory I/O interface does not support full address bus capability, then device complexity is reduced, but random access capability deteriorates
Solution Approach 1:
The buffer memory serves as an intermediary that provides full random access capability to the host while the flash memory maintains its simplified I/O interface. The buffer receives sequential data from the flash memory and provides random access to the host, effectively hiding the limitation of the flash interface from the host system.
Solution Approach 2:
The system is segmented into three functional layers: the simplified flash memory interface, the buffer memory layer that provides translation and random access capability, and the host interface. This segmentation allows each layer to operate at its optimal complexity level without compromising the others.
3Reliability
If sequential page-by-page data transfer is used, then data integrity is improved, but transfer time deteriorates
Solution Approach 1:
The buffer memory enables continuous data transfer by maintaining a persistent storage area where data can be read and written without interruption. The buffer allows the flash memory to operate continuously in sequential mode while the host can access data randomly, eliminating idle time between sequential operations and maintaining continuous useful action throughout the transfer process.
Data Source
AI summary
Described embodiments provide for transferring data from one location to another location in a memory of a media controller. A transmit data path and a receive data path of the media controller are linked with a generic direct memory access (GDMA). The transmit data path includes a transmit (TX) buffer and the receive data path includes a receive (RX) buffer. The GDMA is programmed with a total transfer count and a transfer mode. The GDMA processes the movable data based on the total transfer count and the transfer mode by converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with status entries, which translates frames of the moveable data between the TX data path and the RX data path and synchronizes the movable data between the TX buffer and the RX buffer with the status entries.