Gate Driver On Array Shift Register Clock Control
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Solution Overview
Problem
Existing gate driver on array technologies for display devices have fixed scanning times for each row of pixel units due to a fixed frequency of the clock signal, leading to monotonous driving approaches and limited flexibility.
Innovation Solution
A shift register unit comprising two clock control circuits that alternately output clock signals with the same frequency but different phases, allowing for adjustable charging times and enriched driving approaches by controlling the output circuit to provide driving signals with varying frequencies and duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed frequency clock signal is used to drive the shift register unit, then the scanning time for each row of pixel units is fixed, but the driving approach becomes monotonous and lacks flexibility
Solution Approach 1:
The clock signal generation is segmented into multiple independent clock control circuits (first clock control circuit and second clock control circuit), each capable of independently controlling different clock signals (first clock signal and second clock signal). This segmentation allows flexible combination of clock signals to achieve variable scanning times without requiring a completely new clock generation system.
Solution Approach 2:
The patent introduces dynamic control capability by allowing the clock control circuits to selectively output different clock signals based on control signals. The scanning time becomes dynamic and adjustable rather than fixed, enabling the system to adapt to different display requirements by changing the clock signal frequency or duty cycle on-the-fly.
2Productivity
If the clock signal frequency is increased to reduce scanning time, then productivity improves, but power consumption increases
Solution Approach 1:
The patent changes the clock signal parameters (frequency, duty cycle) dynamically based on display requirements. For high-resolution displays requiring longer charging times, lower frequency or adjusted duty cycle clock signals are used, reducing power consumption. For faster scanning requirements, higher frequency clock signals are employed. This parameter adjustment capability allows optimization of the trade-off between scanning speed and power consumption.
Solution Approach 2:
The patent utilizes periodic clock signals with adjustable periods and duty cycles to control the charging of pixel units. By varying the periodic characteristics of the clock signals, the system can achieve different scanning speeds and charging times, allowing flexible adjustment of productivity versus power consumption based on display mode and resolution requirements.
3Reliability
If the scanning time is extended to improve charging completeness, then display quality improves, but the frame rate decreases
Solution Approach 1:
The scanning time is made dynamic and adjustable through the clock control circuits. The system can extend scanning time when high display quality and complete pixel charging are required, and reduce scanning time when high frame rate is the priority. This dynamic adjustment allows flexible optimization between charging completeness and frame rate based on real-time display requirements.
Solution Approach 2:
The patent changes clock signal parameters (frequency, duty cycle) to control the duration and effectiveness of pixel charging. By adjusting these parameters, the system can achieve adequate charging completeness at various scanning speeds, allowing trade-off optimization between display quality and frame rate without being constrained by a fixed scanning time.
Data Source
AI summary
A shift register unit, a driving method, a gate driver on array and a display device. The shift register unit includes: a first clock control circuit, a second clock control circuit, an output control circuit and an output circuit. The first clock control circuit is configured to, under control of a second control signal from a second control signal terminal, a third clock signal from a third clock signal terminal, and a fourth clock signal from a fourth clock signal terminal, alternately output a second clock signal from a second clock signal terminal and a first clock signal from a first clock signal terminal to the output control circuit. The second clock control circuit is configured to alternately output the first clock signal and the second control signal to the output circuit under control of the second control signal, the third clock signal and the fourth clock signal.