Ge Channel Semiconductor Device for 3D Stacking
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Solution Overview
Problem
Current semiconductor technologies face limitations in increasing wiring density due to the large area penalty and high manufacturing costs associated with Through Silicon Vias (TSV) and the inferior performance of a-Si-TFT CMOS, which fails to enhance performance and reduce power consumption effectively in three-dimensional stacking.
Innovation Solution
A semiconductor device with a Ge channel is implemented, featuring a CMOS circuit with a Ge-CMOS layer above an Si-CMOS layer, using poly-Ge channels and work function control layers to enable dynamic threshold control and adaptive power management, reducing process temperature and manufacturing costs while improving performance and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through Silicon Vias (TSV) are used for three-dimensional stacking, then wiring connection density can be increased, but area penalty and manufacturing cost increase significantly
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked architecture, enabling vertical interconnects that multiply wiring capacity without increasing chip footprint. Multiple active layers are stacked vertically with through-silicon vias providing inter-layer connections, effectively utilizing the third dimension to increase wiring density while maintaining compact form factor.
2Productivity
If Through Silicon Vias (TSV) are used for three-dimensional stacking, then wiring connection density can be increased, but manufacturing cost increases
Solution Approach 1:
The patent optimizes TSV parameters including diameter (50-200 nm), spacing (100-500 nm), and depth to balance performance and manufacturability. The via diameter and spacing are carefully controlled to achieve high density while remaining compatible with existing fabrication processes, reducing overall manufacturing complexity and cost.
3Device complexity
If a-Si-TFT CMOS is used in three-dimensional stacking, then device integration is achieved, but performance is markedly inferior and power consumption is high
Solution Approach 1:
The patent employs a hybrid architecture combining a-Si-TFT devices in upper layers with Ge-channel MOSFETs in lower layers. The a-Si-TFT provides adequate performance for upper-layer logic while the high-mobility Ge-channel devices in lower layers provide strong driving current and low leakage, achieving overall high performance and low power consumption through material composition optimization.
4Device complexity
If a-Si-TFT CMOS is used in three-dimensional stacking, then device integration is achieved, but power consumption is not reduced sufficiently
Solution Approach 1:
The patent changes the channel material parameter from a-Si to Ge in lower-layer devices, exploiting Ge's superior carrier mobility to reduce on-resistance and improve current driving capability. This parameter change enables lower operating voltages and reduced dynamic power consumption while maintaining high integration density.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.