Germanium-Doped HEMT Epitaxy for Sharp Layer Edges
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for manufacturing HEMT transistors face challenges in achieving sharp layer edges and precise alignment, leading to higher series resistances and reduced transistor performance due to issues like morphology accidents and mediocre reproducibility with silicon-doped GaN epitaxy.
Innovation Solution
A method involving a high-temperature epitaxial growth process using Germanium-doped hexagonal crystal semiconductor material, where the growth zone corresponds to openings in a masking layer, allowing for sharper edges and precise alignment of gate electrodes relative to ohmic source and drain contacts, thereby reducing series resistances and improving transistor gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If silicon-doped GaN epitaxial growth is used to define source and drain locations, then transistor dimensions can be reduced, but morphology defects such as SiN precipitates, uneven layer heights, and poor reproducibility occur
Solution Approach 1:
The patent changes the doping element from silicon to germanium in the GaN epitaxial growth. Germanium doping avoids the mass transport issues and morphology defects associated with silicon doping, while still enabling low-temperature growth and small transistor dimensions. This parameter change (doping element) resolves the contradiction between miniaturization and manufacturing precision.
2Manufacturing precision
If low-temperature epitaxial growth is used to prevent mass transport, then morphology defects are avoided, but the GaN layer thickness must be kept small to avoid exceeding the dielectric layer
Solution Approach 1:
The patent changes the doping element from silicon to germanium, which has different diffusion characteristics. Germanium-doped GaN can be grown at low temperatures without significant mass transport, but unlike silicon-doped GaN, it does not require strict thickness limitations to prevent dielectric layer exposure. This parameter change enables both good morphology and adequate thickness control.
3Manufacturing precision
If high-temperature epitaxial growth with germanium doping is used, then sharper edges and better alignment are achieved, but mass transport may occur
Solution Approach 1:
The patent uses germanium doping in GaN epitaxial growth, which enables high-temperature processing without the severe mass transport problems associated with silicon doping. The germanium-doped GaN maintains compositional stability even at elevated temperatures, allowing sharp edges and precise alignment to be achieved while preventing excessive material redistribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method results in sharper epitaxial layer edges, enabling lower series resistances, higher power efficiency, and increased transconductance, with Germanium-doped material having a crystalline structure that allows for thicker growth layers without increasing complexity, and reduces the need for additional masking steps.
Implementation Method 1
grow by high-temperature epitaxial growth a hexagonal crystal semiconductor material Ga(1-x'-y')Al(x')In(y')N doped with germanium
Data Source
Figure 1~3
Figure 4~5
Figure 6
AI summary
The invention relates to a method for manufacturing a heterojunction field-effect transistor. Said transistor includes a semiconductor structure made of stacked layers. Said method includes: providing a buffer layer (2), a channel layer (3), and a barrier layer (4) on a substrate layer (1), which are all produced with Ga(1-p-q)Al(p)In(q)N hexagonal crystal materials; forming an opening in a dielectric masking layer (5) deposited on the barrier layer; growing, using high-temperature epitaxy, a Germanium-doped Ga(1-X'-y')Al(X')In(y')N hexagonal crystal semiconductor material (6, 6') on a growth area defined by the opening formed in the masking layer; and depositing a source or drain contact electrode (15, 16) onto the material, thus deposited via epitaxy, and depositing a gate electrode (13) at a location outside the growth area.