Ge Fin Structure with SiGe Buffer for Mobility and Leakage Control
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Solution Overview
Problem
Ge-FinFETs face issues such as non-uniform channel plane orientation, variation in threshold voltage, and leakage current due to limitations in applying stress to the channel and fin structure, particularly in narrow fin widths and pitches, which affect mobility and reliability.
Innovation Solution
A semiconductor device with a Ge- or SiGe-fin structure is developed, featuring a convex-shaped active area on a Si substrate with a relaxed SiGe buffer layer and a strained Ge fin structure, where compressive stress is applied through a relaxed SiGe layer acting as a stressor, and the Ge fin structure is selectively etched to achieve a (110) plane orientation, reducing threading dislocations and enhancing mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If Ge layer is epitaxially grown on recessed Si substrate region after forming STI, then FinFET structure is formed, but channel plane orientation becomes non-uniform due to tapered shape causing mobility deterioration
Solution Approach 1:
A (110)-oriented Si layer is formed in advance in the fin region before Ge layer growth. This preliminary layer ensures that the channel plane orientation is predetermined and uniform, preventing the orientation non-uniformity that would otherwise occur due to the tapered shape from STI processing.
2Productivity
If fin width and pitch are reduced to 50 nm and 150 nm respectively, then device miniaturization is achieved, but stress application to channel becomes difficult due to limited space in S/D region
Solution Approach 1:
A (110)-oriented Si layer is introduced as an intermediary layer between the Ge fin structure and the underlying substrate. This intermediary layer serves dual purposes: it maintains the miniaturized fin dimensions while providing a platform for effective stress application through its specific crystal orientation, thereby resolving the space limitation issue.
3Force
If stressor is inserted into underlying layer, then stress can be applied to channel, but stressor is processed by fin etching making strain application inefficient
Solution Approach 1:
The (110)-oriented Si layer is formed preliminarily in the fin region before any etching or stressor insertion steps. This pre-formed layer with its specific orientation enables subsequent stress application to be more efficient, as the crystal structure inherently facilitates strain transfer to the Ge fin channel without being removed during fin etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves mobility, reduces threshold voltage variation, and minimizes leakage current by efficiently applying strain and reducing interface roughness, while maintaining a large stressor volume even in miniaturized devices, resulting in high-performance pMOSFETs with enhanced current driving ability.
Implementation Method 1
a buffer layer of Si1-xGex (0<x≤1) and a fin structure of Si1-yGey (y≤x) having a (110) plane on a side surface which is an etching side surface
Implementation Method 2
the Ge fin structure is selectively etched to achieve a (110) plane orientation, reducing threading dislocations and enhancing mobility
Implementation Method 3
reducing threading dislocations and enhancing mobility
Data Source
AI summary
According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y≦1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.