Non-Selective Epitaxial Deposition for Ge NMOS Transistors
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Solution Overview
Problem
The fabrication of Ge-rich n-MOS transistors is challenging due to the diffusion of n-type dopants like phosphorous and arsenic into the Ge channel and adjacent insulator regions during high-temperature semiconductor fabrication processes, leading to poor S/D contact resistance and performance degradation, especially in sub-30 nm technology.
Innovation Solution
A non-selective epitaxial source/drain deposition process is employed at reduced temperatures (450 to 600 degrees C) to prevent n-type dopant diffusion into the Ge channel, resulting in the formation of mono-crystalline Si:P or SiGe:P layers on S/D regions and amorphous Si:P or SiGe:P layers on shallow trench isolation and contact trench sidewall surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-temperature fabrication processes are used, then semiconductor fabrication can proceed efficiently, but n-type dopant diffuses into the Ge channel and adjacent insulator regions causing performance degradation
Solution Approach 1:
The patent changes the temperature parameter from high-temperature (conventional) to low-temperature (450-600°C) epitaxial deposition to suppress dopant diffusion while maintaining fabrication efficiency. This parameter change directly addresses the contradiction by enabling dopant distribution control without sacrificing productivity
Solution Approach 2:
The patent applies non-selective epitaxial deposition that creates different material phases (amorphous vs. crystalline) in different locations based on local conditions. The amorphous SiGe:P forms in isolation regions while crystalline SiGe:P forms in source/drain regions, achieving local quality differentiation that prevents dopant diffusion into the channel
2Reliability
If n-type dopant is introduced at high concentrations to improve contact resistance, then source/drain contact performance improves, but dopant diffuses into the Ge channel causing performance degradation
Solution Approach 1:
The patent introduces n-type dopant at high concentrations during low-temperature epitaxial deposition, which prevents dopant diffusion into the Ge channel while maintaining high dopant levels at source/drain regions for low contact resistance. The low temperature parameter change is key to achieving both objectives simultaneously
Solution Approach 2:
The patent uses amorphous SiGe:P as an intermediary material that forms between the dopant source and the Ge channel. This amorphous phase acts as a barrier that prevents dopant diffusion into the channel while still allowing high dopant concentration to be maintained in the source/drain contact regions
3Manufacturing precision
If selective epitaxial deposition is used to deposit dopant only in source/drain regions, then dopant placement precision improves, but process complexity increases
Solution Approach 1:
Instead of using selective epitaxial deposition that requires complex masking and patterning steps, the patent inverts the approach by using non-selective epitaxial deposition followed by differential phase formation. The amorphous/crystalline phase differentiation occurs naturally based on local conditions, achieving dopant placement precision without increasing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces n-type dopant diffusion, enhancing the performance of Ge-rich n-MOS transistors by maintaining higher dopant levels at the source/drain regions, thereby improving contact resistance and transistor performance even at smaller critical dimensions.
Implementation Method 1
A non-selective epitaxial source/drain deposition process is employed at reduced temperatures (450 to 600 degrees C) to prevent n-type dopant diffusion into the Ge channel
Implementation Method 2
The fabrication of Ge-rich n-MOS transistors is challenging due to the diffusion of n-type dopants like phosphorous and arsenic into the Ge channel and adjacent insulator regions during high-temperature semiconductor fabrication processes
Data Source
AI summary
Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.