Ge Side Spacer Structure for GAA Mobility and Capacitance Control
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Solution Overview
Problem
Existing gate-all-around (GAA) devices with multi-channels face challenges in enhancing transistor driving ability and carrier mobility, while also needing to reduce parasitic capacitance between gate structures and source/drain regions.
Innovation Solution
Incorporation of germanium (Ge) and germanium oxide (GeO) as side spacer patterns in the semiconductor device, providing lattice stress to source/drain and channel regions, and increasing the distance between gate structures and source/drain regions to improve carrier mobility and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional spacer materials are used in gate-all-around structures, then device structure is maintained, but carrier mobility is limited and parasitic capacitance is high
Solution Approach 1:
The patent changes the material parameter of the spacer from conventional materials (such as silicon oxide or silicon nitride) to germanium (Ge) and germanium oxide (GeO). This material substitution introduces lattice stress effects that enhance carrier mobility in the channel and source/drain regions, directly resolving the performance limitations without increasing device structural complexity
Solution Approach 2:
The patent employs a composite structure where germanium and germanium oxide are used in specific combinations and sequences. The germanium layer provides lattice stress for carrier mobility enhancement, while the germanium oxide layer provides insulating properties to reduce parasitic capacitance. This composite material approach simultaneously addresses both carrier mobility and parasitic capacitance issues
2Area of stationary object
If gate structures are positioned closer to source/drain regions, then device area is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent introduces germanium oxide (GeO) as an intermediary material between the gate structure and the source/drain regions. This GeO layer acts as a mediator that provides electrical insulation, effectively reducing parasitic capacitance while allowing the gate to be positioned close to the source/drain regions. This resolves the contradiction by enabling close spacing without the harmful capacitance effect
Solution Approach 2:
The patent changes the dielectric parameter by using germanium oxide with specific insulating properties in the spacer structure. This material parameter change increases the electrical isolation between the gate and source/drain regions, thereby reducing parasitic capacitance while maintaining compact device geometry
3Reliability
If spacer material lattice stress is increased to improve carrier mobility, then carrier mobility improves, but parasitic capacitance may increase
Solution Approach 1:
The patent segments the spacer structure into distinct functional layers: a germanium (Ge) layer that provides lattice stress for carrier mobility enhancement, and a germanium oxide (GeO) layer that provides insulating properties for parasitic capacitance reduction. This segmentation allows each layer to independently perform its specific function without compromising the other, resolving the contradiction between mobility improvement and capacitance control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances carrier mobility in source/drain and channel patterns, and reduces parasitic capacitance, thereby improving the performance of the semiconductor device.
Implementation Method 1
The first side spacer patterns include germanium (Ge)... provide lattice stress and improve carrier mobility
Implementation Method 2
forming second side spacer patterns on inner side surfaces of the first side spacer patterns by performing an oxidation process... The second side spacer patterns include germanium oxide (GeO)
Implementation Method 3
forming source/drain regions on outer side surfaces of the first side spacer patterns and the channel patterns by performing an epitaxial process
Data Source
AI summary
A semiconductor device includes source/drain regions formed over a substrate, and channel patterns and gate structures formed between the source/drain regions in a horizontal direction. The channel patterns are arranged to be spaced apart from each other over a surface of the substrate in a vertical direction. The gate structures are disposed between the channel patterns in the vertical direction. The gate structures include the following: side spacer patterns formed adjacent to the source/drain regions in the first horizontal direction, interfacial insulating layers formed over upper and lower surfaces of the channel patterns, gate insulating layers over surfaces of the side spacer patterns and surfaces of the interfacial insulating layers, and gate electrodes over the gate insulating layers. The side spacer patterns include germanium (Ge).