Generalized QED Framework for Hardware Accelerator Verification
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Solution Overview
Problem
Existing formal verification methodologies for hardware accelerators (HAs) struggle to efficiently verify interfering HAs, which have outputs dependent on the outputs of other actions, violating the functional consistency checking of Accelerator Quick Error Detection (A-QED).
Innovation Solution
A general formal verification methodology, referred to as General Quick Error Detection (G-QED), is introduced. G-QED uses bounded model checking to verify hardware processing circuit designs by checking functional consistency, single-action checking, and response bounds, applicable to both interfering and non-interfering actions without requiring extensive design-specific properties or full functional specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If A-QED functional consistency checking is used to verify non-interfering HAs, then verification simplicity and speed are improved, but the methodology cannot handle interfering HAs whose outputs depend on other actions
Solution Approach 1:
The verification process is segmented into three distinct phases: (1) extracting action sequences from the HA design, (2) generating functional consistency properties by comparing actions with identical inputs, and (3) verifying these properties using bounded model checking. This segmentation allows the methodology to handle interfering HAs systematically by breaking down the complex verification into manageable steps, each addressing specific aspects of functional consistency without requiring complete design specifications.
2Reliability
If traditional formal verification methods are used to verify interfering HAs, then verification thoroughness is improved, but the effort required to craft design-specific properties and full functional specifications becomes tremendous and time-consuming
Solution Approach 1:
The verification methodology is self-service in nature, automatically extracting action sequences and generating functional consistency properties from the HA design without requiring manual intervention to craft verification properties. The system autonomously identifies actions with identical inputs, formulates consistency checks, and executes verification using bounded model checking, thereby eliminating the time-consuming manual property crafting process while maintaining thorough verification of interfering HAs.
3Ease of operation
If A-QED self-consistency checks are used, then verification simplicity is improved by not requiring extensive design-specific properties, but the methodology fails for interfering HAs that read or write outputs of other actions at dependent clock cycles
Solution Approach 1:
The methodology dynamically adapts to different HA types by automatically analyzing the temporal and data dependencies between actions. It identifies interfering actions that read or write outputs of other actions at dependent clock cycles and generates appropriate functional consistency properties for each case. This dynamic adaptation allows the same verification framework to handle both non-interfering and interfering HAs, as well as actions with complex clock cycle dependencies, without requiring manual configuration or design-specific properties.
Data Source
AI summary
Systems and methods of verifying a hardware processing circuit design for a digital system are disclosed. Three different computer models of the same hardware are implemented. The first computer model is implemented on a first sequence of action inputs and a second sequence of action inputs. The second computer model is implemented on the first sequence of action inputs and is allowed to idle until the first sequence is done. The architectural states of the second computer model are then recorded. The third computer model is implemented on the second sequence after having set the third computer model to the recorded architectural states. The outputs of the first computer model and the third computer model are implemented to check for functional consistency. The techniques described herein can be used to check digital designs for functional consistency, are sound and complete, and do not require an understanding of implementation details.