Generational Physical Address Proxies for L2 Cache Coherency

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Solution Overview

Problem

Cache memories in microprocessors face challenges in reducing access time and improving cache coherency, particularly in multi-processor systems, where the overhead of cache coherence protocols and the storage of additional information impact performance.

Innovation Solution

Implementing a physically-indexed, physically-tagged second-level set-associative cache that uses generational identifiers and physical address proxies to efficiently manage cache misses and coherency, reducing the need for direct comparisons of physical memory line addresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cache memories store additional information for cache coherency protocols, then cache coherency is maintained across multi-processor systems, but cache access time increases and performance deteriorates

Engineering Contradiction:
Improvecache coherencyVSAvoidcache access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The physical address is segmented into a physical address proxy (PAP) portion and a generational identifier (GENID) portion. The PAP contains the set index and way information needed for cache location identification, while the GENID tracks cache line generations. This segmentation allows the cache to maintain coherency information without storing complete physical addresses, reducing access time while preserving coherency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of storing complete physical addresses in the cache, the invention creates a simplified copy or proxy representation (PAP) that contains only the essential addressing information needed for cache operations. This copying approach maintains the necessary coherency tracking while significantly reducing the time required for address comparison and cache access.

Inventive Principle:
Principle #26Copying

2Reliability

If cache memories store complete physical addresses for coherency protocols, then cache coherency is ensured, but the physical size of the cache increases

Engineering Contradiction:
Improvecache coherencyVSAvoidcache physical size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention extracts only the essential components of the physical address needed for cache operations (set index and way information) and places them in the PAP. The remaining address information is handled separately through the GENID mechanism. This extraction reduces the amount of data stored in each cache entry, thereby reducing the physical cache size while maintaining coherency capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The PAP acts as an intermediary structure that mediates between the complete physical address and the cache entry storage. Instead of storing full physical addresses, the PAP provides a compact representation that enables coherency protocols to function with reduced storage requirements, effectively bridging the gap between coherency needs and space constraints.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If cache memories use traditional physical address storage, then address matching is straightforward, but cache access time and processor cycle time increase

Engineering Contradiction:
Improveaddress matchingVSAvoidprocessor cycle time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The invention changes the parameters used for address matching by replacing complete physical address comparison with PAP-based indexing combined with GENID verification. This parameter transformation enables faster access by using the compact PAP for initial location identification and the GENID for generation validation, significantly reducing the time required for address matching while maintaining correctness.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11860794B2Generational physical address proxies
Publication Date: 2024.01.02 VENTANA MICRO SYSTEMS INC
  • US11860794B2 patent drawing
  • US11860794B2 patent drawing
  • US11860794B2 patent drawing

AI summary

Each PIPT L2 cache entry is uniquely identified by a set index and a way and holds a generational identifier (GENID). The L2 detects a miss of a physical memory line address (PMLA). An L2 set index is obtained from the PMLA. The L2 picks a way for replacement, increments the GENID held in the entry in the picked way of the selected set, and forms a physical address proxy (PAP) for the PMLA with the obtained set index and the picked way. The PAP uniquely identifies the picked L2 entry. The L2 forms a generational PAP (GPAP) for the PMLA with the PAP and the incremented GENID. A load/store unit makes available the GPAP as a proxy of the PMLA for comparisons with GPAPs of other PMLAs, rather than making comparisons of the PMLA itself with the other PMLAs, to determine whether the PMLA matches the other PMLAs.