Generative AI Hardware Mapping via Multi-Level Simulation
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Solution Overview
Problem
The challenge of efficiently mapping generative giant artificial intelligence models to dedicated hardware structures like FPGA/ASIC is exacerbated by the disparity between software and hardware development speeds, particularly due to the large model size, which slows down the hardware development process.
Innovation Solution
A method involving sequential source code, instruction level, and register transfer level simulations, utilizing GPU for code level and instruction level simulations, and multithread loading to efficiently map generative AI models to hardware, including cross-verification and module-level testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional RTL simulation is used for hardware mapping of generative AI models, then verification accuracy is maintained, but development speed deteriorates due to large model size
Solution Approach 1:
The patent divides the verification process into three distinct simulation levels: source code level simulation, instruction level simulation, and register transfer level simulation. Each level handles specific aspects of the hardware mapping process, allowing parallel processing and reducing the overall time required for complete verification while maintaining accuracy at each stage.
Solution Approach 2:
The patent performs source code level simulation and instruction level simulation before executing register transfer level simulation. These preliminary simulations prepare and validate the model at higher abstraction levels, identifying issues early in the design process before committing to time-consuming RTL simulation, thereby reducing total development time.
2Productivity
If software development speed is increased to keep pace with hardware development, then model iteration improves, but hardware mapping efficiency deteriorates due to size mismatch
Solution Approach 1:
The patent implements a dynamic, multi-level simulation framework that adapts to different stages of hardware mapping. The system automatically transitions between source code level, instruction level, and register transfer level simulations based on the current design stage and requirements, providing flexible verification that scales with software development iterations without compromising hardware mapping efficiency.
3Reliability
If comprehensive verification is performed at all simulation levels, then reliability is improved, but device complexity increases
Solution Approach 1:
The verification system is segmented into three distinct simulation levels, each with specific tools and methodologies tailored to that stage. This segmentation allows comprehensive verification without requiring a single complex verification system, as each level can be independently configured and executed with appropriate tools.
Solution Approach 2:
The patent introduces instruction level simulation as an intermediary between source code level and register transfer level simulations. This intermediate layer acts as a mediator that translates high-level instructions into hardware-specific operations, simplifying the transition and reducing the complexity of direct RTL verification while maintaining comprehensive coverage.
Data Source
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AI summary
Provided are an efficient hardware mapping method and system for a generative largescale artificial intelligence model. The hardware mapping method, according to one embodiment, may comprise the steps of: receiving model software; and, by means of at least one processor, sequentially performing a source code level simulation, an instruction level simulation, and a register transfer level simulation with respect to the model software.