Generative AI Model Hardware Mapping With Staged Simulation
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Solution Overview
Problem
The rapid distribution of generative artificial intelligence models to dedicated hardware structures like FPGA/ASIC is hindered by the disparity between software and hardware development speeds, particularly for models with sizes exceeding 1 billion units, which slows down the mapping process.
Innovation Solution
A method involving sequential source code, instruction level, and register transfer level simulations, utilizing GPUs for code level and instruction level simulations, and multithread loading to efficiently map generative giant AI models to hardware, with optional hardware module addition and modular test case writing for register transfer level verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If generative giant AI models are mapped to dedicated hardware structures, then hardware acceleration and performance are improved, but the mapping process becomes excessively slow due to model size exceeding 1 billion units
Solution Approach 1:
The patent segments the verification process into three distinct simulation levels: source code level simulation, instruction level simulation, and register transfer level simulation. Each level verifies different aspects of the hardware mapping, allowing parallel processing and reducing the overall verification time for giant AI models with 1 billion+ units.
Solution Approach 2:
The patent performs preliminary source code level simulation and instruction level simulation before executing the resource-intensive register transfer level simulation. This preliminary verification identifies and resolves issues early in the design process, preventing costly rework during later stages and accelerating the overall mapping process.
2Reliability
If comprehensive verification is performed for hardware mapping, then reliability and correctness are improved, but development speed decreases due to extensive simulation requirements
Solution Approach 1:
The verification process is divided into three segmented simulation levels, each with specific verification objectives. Source code level simulation verifies architectural correctness, instruction level simulation verifies functional correctness, and register transfer level simulation verifies implementation correctness. This segmentation allows comprehensive verification while enabling parallel execution to maintain development speed.
Solution Approach 2:
The patent applies partial verification at each simulation level, focusing on critical paths and high-risk areas rather than exhaustive verification of all model components. This selective verification approach maintains high reliability for the most important functions while reducing overall verification time and resource consumption.
3Measurement precision
If multiple simulation levels are executed sequentially, then verification thoroughness is improved, but processing time increases significantly
Solution Approach 1:
The patent segments the verification into three independent simulation levels that can be executed in parallel or with minimal sequential dependency. Each simulation level operates on different data representations and verification criteria, allowing simultaneous execution on different hardware resources to reduce total processing time while maintaining comprehensive verification thoroughness.
4Adaptability or versatility
If hardware modules are added to existing hardware structure, then model implementation capability is improved, but hardware complexity increases
Solution Approach 1:
The patent designs hardware modules with universal interfaces and standardized communication protocols that allow the same module to support multiple AI model architectures and configurations. This multi-functionality approach enables the hardware structure to adapt to different models without proportionally increasing complexity, as single modules can serve multiple purposes across different verification scenarios.
Data Source
AI summary
Provided is a method and system for efficient hardware mapping of a generative giant artificial intelligence model. A hardware mapping method may include receiving, by at least one processor, model software and sequentially performing, by the at least one processor, source code level simulation, instruction level simulation, and register transfer level simulation for the model software.