Generic Memory Models for VLSI Design Optimization
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Solution Overview
Problem
In VLSI design, memory optimization is challenging due to the long and expensive design cycle, where memory selection made early in the process limits flexibility and hinders taking advantage of increasing design choices, leading to suboptimal performance, area, and power consumption.
Innovation Solution
Implementing generic memory models in the RTL description of IC designs, allowing memory instances to be optimized by changing parameters without modifying the RTL description, using a generic memory call interface with specific models generated for simulation, timing, and layout phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory selection is made early in the design process and coded into the RTL description, then the design process becomes stable and verified, but flexibility to change memory options is lost and design cycle disruption occurs
Solution Approach 1:
The patent segments the memory configuration into two parts: the stable RTL description that defines the logical interface, and the parameterizable memory model that can be changed independently. This allows the memory selection to be optimized later in the design cycle without affecting the verified RTL code, resolving the contradiction between stability and adaptability.
Solution Approach 2:
The patent introduces a generic memory model as an intermediary between the RTL description and the actual memory implementation. This intermediary layer allows parameter changes (depth, data width, pipeline status) to be applied without modifying the RTL, thus maintaining design stability while enabling flexibility in memory selection.
2Productivity
If memory parameters are changed after RTL description is finalized, then optimization opportunities are captured, but the design flow is disrupted and re-verification is required
Solution Approach 1:
The patent makes the memory model dynamic and parameterizable, allowing depth, data width, and other characteristics to be changed without regenerating the RTL description. This dynamic approach enables continuous optimization throughout the design cycle without the time loss associated with re-verification of modified RTL code.
Solution Approach 2:
The patent enables optimization by changing memory parameters (depth, data width, pipeline status) as configurable values rather than requiring structural changes to the RTL description. This parameter-based approach maintains design flow continuity and eliminates the need for re-verification, thus improving productivity without time loss.
3Adaptability or versatility
If multiple memory options from different suppliers are explored, then better PPA trade-offs are achieved, but the complexity of evaluating and switching between options increases
Solution Approach 1:
The patent creates a universal memory model that can represent different memory types and suppliers through a single interface. The generic memory model accommodates various configurations (depth, data width, pipeline status) and can be instantiated for different memory options without requiring separate evaluation procedures, thus reducing complexity while maintaining versatility.
Solution Approach 2:
The patent simplifies the evaluation and switching process by using parameter changes (depth, data width, pipeline status) to explore different memory options. Instead of complex evaluation procedures, the system can quickly switch between memory suppliers and configurations by modifying these parameters, reducing evaluation complexity while maintaining option flexibility.
Data Source
AI summary
Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.