Genetic Optimization for Via Placement in Multi-Layer PCB Routing

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Solution Overview

Problem

Current Electronic Design Automation (EDA) tools are inefficient in understanding the relationship between component placement and via placement, leading to slow and inefficient routing processes, particularly in complex multi-layer PCB designs, and are unable to effectively integrate via placement into the design workflow.

Innovation Solution

A computer-implemented method using genetic optimization to determine the placement of vias by receiving pin and net information, generating a crossing map, performing crossover and mutation operations, and evaluating fitness based on metrics such as crossing distribution and uniformity, which allows for faster and more efficient via placement and routing strategies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional EDA tools are used for routing, then routing can be performed, but the process is slow and inefficient particularly in complex multi-layer PCB designs

Engineering Contradiction:
Improverouting efficiencyVSAvoiddesign synthesis time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the routing problem into distinct phases: via placement optimization using genetic algorithms, and subsequent routing execution. By separating via placement from routing, the system can optimize via locations independently to minimize crossings and improve routing efficiency, directly addressing the slow performance of traditional integrated EDA tools in complex multi-layer designs

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic optimization through genetic algorithms that iteratively evolve via placement solutions. The system dynamically adjusts via positions based on fitness evaluations of crossing minimization, enabling adaptive optimization rather than static routing approaches. This dynamic process continues until convergence or time constraints are met, significantly improving routing efficiency for complex designs

Inventive Principle:
Principle #15Dynamics

2Extent of automation

If automatic placement and routing tools are used, then routing can be automated, but the tools are often faulty and produce unprofessional results

Engineering Contradiction:
Improveautomation of placement and routingVSAvoidquality of routing results
Core Design Contradiction:
Extent of automationVSReliability

Solution Approach 1:

The patent performs preliminary via placement optimization before actual routing execution. By pre-optimizing via locations using genetic algorithms to minimize crossings and improve signal integrity, the system creates a foundation for high-quality routing results. This preliminary action ensures that subsequent routing operates from an optimized via configuration, improving both professionalism and reliability of automated results

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through fitness evaluations that assess via placement quality based on crossing minimization and signal integrity metrics. The genetic algorithm uses this feedback to iteratively improve via placements, ensuring that automated tools produce reliable, professional-grade results rather than faulty outputs. The feedback loop continues until optimal or near-optimal solutions are achieved

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11803760B1Method and systems for combining neural networks with genetic optimization in the context of electronic component placement
Publication Date: 2023.10.31 CADENCE DESIGN SYST INC
  • US11803760B1 patent drawing
  • US11803760B1 patent drawing
  • US11803760B1 patent drawing

AI summary

The present disclosure relates to applying genetic optimization to a routing strategy associated with an electronic design. Embodiments may include receiving pin and net information from an electronic design file and determining a minimum spanning tree for all pins associated with each net. Embodiments may include identifying pairs of connected pins and representing the pins as at least one line segment without layer information. Embodiments may include generating a crossing map based upon the line segments and assigning random layer information to each of the line segments. Embodiments may further include performing crossover and mutation operations to the line segments using hyperparameters and evaluating a fitness of the line segments. Embodiments may also include instantiating vias based upon a layer to which the line segment was assigned.