Genetic Via Placement Solver for Multi-Layer PCB Signal Density
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Solution Overview
Problem
The existing manufacturing constraints for printed circuit boards (PCBs) limit signal density due to the minimum drilling distance required for back-drilling signal vias, which can damage the PCB and restrict the minimum pitch, leading to sharp resonances in high-speed signals.
Innovation Solution
A method using a genetic via placement solver to iteratively evaluate and adjust the placement of signal vias in a multi-layer circuit board, allowing for shifted positions that meet placement criteria, thereby reducing stubs and increasing signal density without violating manufacturing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If signal vias are placed closer together to increase signal density, then signal density improves, but the minimum drilling distance constraint is violated increasing PCB damage risk
Solution Approach 1:
The patent introduces a genetic algorithm-based via placement solver that optimizes via positions in multiple dimensions (x, y coordinates across multiple layers) to find configurations that satisfy both minimum pitch constraints and signal density requirements. This computational optimization approach enables finding non-intuitive via placements that maximize density while respecting manufacturing constraints.
Solution Approach 2:
The system dynamically adjusts via placement parameters (positions, depths, diameters) and back-drilling parameters (depths, offsets) to optimize signal density while maintaining minimum pitch distances. The genetic algorithm iteratively modifies these parameters to find optimal configurations that balance density and manufacturability.
2Reliability
If back-drilling is performed to remove stubs, then signal quality improves, but the minimum pitch constraint limits signal density
Solution Approach 1:
The via placement solver performs preliminary optimization of via positions before the back-drilling process, ensuring that vias are positioned to allow effective stub removal while maintaining acceptable signal density. The genetic algorithm pre-calculates optimal via placements that facilitate subsequent back-drilling operations.
Solution Approach 2:
The patent introduces a computational via placement solver as an intermediary between design requirements and manufacturing constraints. This solver mediates by finding optimal via configurations that satisfy both signal quality requirements (enabling back-drilling) and density requirements, acting as a bridge between conflicting objectives.
3Ease of manufacture
If via placement follows traditional constraints, then manufacturing reliability is maintained, but signal density under chips is limited
Solution Approach 1:
The patent replaces traditional mechanical/conventional via placement rules with a computational genetic algorithm system. This substitution enables exploration of non-traditional via configurations that maintain manufacturing reliability through constraint-based optimization while achieving higher signal densities that would be impossible with rule-based placement.
Solution Approach 2:
The via placement solver performs self-optimization by automatically evaluating and adjusting via positions based on design constraints and objectives. The genetic algorithm autonomously finds optimal configurations without requiring manual intervention, enabling dense via placement that satisfies both manufacturing and performance requirements.
Data Source
AI summary
One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.