Geometry-Aware Command Scheduling for Non-Volatile Memory
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Solution Overview
Problem
Erase commands in data storage systems take longer to complete than write or read commands, leading to increased latency and potential performance issues due to the unavailability of non-volatile memory during erase operations.
Innovation Solution
Implementing a geometry-aware command scheduling method that queues erase commands if the corresponding die set is in a pending state, scheduling them only when the die set transitions to an idle state, thereby minimizing latency and optimizing system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If erase commands are executed immediately when received, then the memory system processes commands in FIFO order, but the latency of data access commands increases due to the long duration of erase operations
Solution Approach 1:
The system performs preliminary checks of the memory device state before executing erase commands. By checking whether the memory device is in an idle state before queuing an erase command, the system prepares the execution environment in advance, preventing latency issues caused by attempting to execute erase operations during pending commands.
Solution Approach 2:
The command scheduling mechanism dynamically adjusts the execution timing of erase commands based on the real-time state of the memory device. Instead of fixed FIFO processing, the system flexibly queues erase commands only when the memory device transitions to an idle state, optimizing the balance between latency and throughput.
2Loss of time
If erase commands are queued only when the die set is idle, then latency is reduced, but the complexity of command scheduling increases
Solution Approach 1:
The memory system is segmented into multiple die sets, each capable of independent command processing. This segmentation allows the scheduler to make simple binary decisions (idle/not idle) for each die set independently, reducing the overall scheduling complexity while still achieving latency optimization through parallel state monitoring.
3Productivity
If the system monitors the command state of each die set, then erase commands are scheduled optimally, but the overhead of state tracking increases
Solution Approach 1:
The memory device itself provides the state information needed for scheduling through its status registers or feedback mechanisms. The processor queries the idle state of die sets through efficient status checks rather than complex monitoring, allowing the memory subsystem to self-report its readiness for erase operations and minimizing processor overhead.
Data Source
AI summary
Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.