Boron-Doped GeSn Epitaxy with SiGe Buffer for Semiconductor Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing complex semiconductor devices due to increased complexity and defects caused by lattice mismatch between substrate and semiconductor layers, which affect device performance.
Innovation Solution
A method involving the formation of a buffer layer with a lattice constant between the substrate and semiconductor layer to relax lattice mismatch, followed by the use of epitaxial source/drain structures with specific dopant profiles to enhance carrier mobility and reduce defects, including a dopant drive-in process at a low thermal budget to maintain crystallization and achieve compressive strain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer layer with intermediate lattice constant is inserted between substrate and semiconductor layer, then lattice mismatch is relaxed and defects are reduced, but device structure becomes more complex and manufacturing process becomes more complex
Solution Approach 1:
A buffer layer comprising silicon germanium (SiGe) is inserted between the silicon substrate and the germanium tin (GeSn) semiconductor layer. The SiGe buffer layer has a lattice constant that is intermediate between silicon and GeSn, serving as a mediator to gradually transition the lattice structure and reduce the lattice mismatch. This intermediary layer prevents direct contact between the mismatched Si and GeSn interfaces, thereby reducing misfit dislocations and defects while maintaining overall structural integrity.
2Reliability
If a buffer layer with intermediate lattice constant is inserted between substrate and semiconductor layer, then lattice mismatch is relaxed and defects are reduced, but manufacturing process becomes more complex
Solution Approach 1:
The SiGe buffer layer is formed preliminarily before depositing the GeSn semiconductor layer. By pre-establishing the intermediate lattice structure, the subsequent GeSn layer can be deposited with reduced stress and fewer defects. This preliminary action of creating the buffer layer with controlled Ge content (e.g., 10-30% Ge) prepares the substrate surface in advance, making the overall manufacturing process more controllable despite the additional step.
3Reliability
If epitaxial source/drain structures with specific dopant profiles are used, then carrier mobility is enhanced and defects are reduced, but manufacturing process complexity increases
Solution Approach 1:
Specific dopant profiles are applied locally to different regions of the epitaxial source/drain structures. By controlling the spatial distribution and concentration of dopants (such as boron or phosphorus) within the epitaxially grown layers, the patent achieves enhanced carrier mobility in critical regions while maintaining appropriate electrical characteristics in other areas. This localized doping strategy optimizes device performance without requiring uniform complex processing across the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing defects, maintaining single-crystalline structure, and increasing carrier density while reducing contact resistance, thus enhancing the manufacturing efficiency of semiconductor devices.
Implementation Method 1
formation of a buffer layer with a lattice constant between the substrate and semiconductor layer to relax lattice mismatch
Implementation Method 2
performing a solid phase diffusion process to form a doped region in the epitaxy structure
Implementation Method 3
achieve compressive strain
Implementation Method 4
epitaxial source/drain structures with specific dopant profiles to enhance carrier mobility
Data Source
AI summary
A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.