Germanium Barrier Layers for Buried Bit Line Agglomeration
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Solution Overview
Problem
Existing semiconductor device fabrication technologies face challenges in reducing parasitic capacitance between adjacent buried bit lines, which can lead to device malfunction as the distance between bit lines narrows, and the use of metal silicide in buried bit lines is prone to agglomeration, causing structural issues and reduced process margins.
Innovation Solution
The implementation of buried bit lines formed in semiconductor bodies using a BSC process with barrier layers containing germanium to prevent metal silicide agglomeration, reducing parasitic capacitance and maintaining structural integrity by positioning the bit lines between germanium-containing barrier layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent buried bit lines is reduced to increase integration density, then the degree of integration is improved, but parasitic capacitance between bit lines increases causing device malfunction
Solution Approach 1:
A barrier layer containing germanium is introduced as an intermediary substance between adjacent buried bit lines. This barrier layer acts as a spacer that physically separates the bit lines, reducing the parasitic capacitance between them while allowing the bit lines to be positioned closer together for higher integration density.
Solution Approach 2:
The patent changes the physical and chemical parameters of the barrier layer (material composition, thickness, dielectric properties) to optimize the balance between reducing parasitic capacitance and maintaining integration density. By adjusting the germanium content and layer thickness, the parasitic capacitance is controlled while preserving compact bit line spacing.
2Reliability
If metal silicide is used in buried bit lines to reduce resistance, then electrical conductivity is improved, but agglomeration occurs causing structural issues and reduced process margins
Solution Approach 1:
The germanium-containing barrier layer serves as a mediator that prevents direct interaction between adjacent metal silicide regions. This intermediary layer suppresses the agglomeration tendency of metal silicide by providing physical separation and controlling diffusion, thereby maintaining both electrical conductivity and structural integrity.
Solution Approach 2:
The patent employs a composite structure combining metal silicide (for low resistance) with germanium-containing barrier layers (for structural stability). This composite approach allows the metal silicide to provide excellent electrical conductivity while the germanium barrier prevents agglomeration and maintains compositional stability during processing.
3Ease of manufacture
If conventional OSC process is used to connect buried bit lines with semiconductor bodies, then connection is achieved, but parasitic capacitance between adjacent buried bit lines increases
Solution Approach 1:
The barrier layer is formed preliminarily before the OSC process, establishing a fixed separation distance between adjacent buried bit lines in advance. This preliminary action ensures that when the OSC process connects the bit lines to semiconductor bodies, the parasitic capacitance is already minimized by the pre-positioned barrier layer.
Solution Approach 2:
The germanium-containing barrier layer acts as a mediator that maintains optimal spacing between buried bit lines during the OSC process. This intermediary structure enables the connection process to proceed effectively while continuously suppressing parasitic capacitance through physical separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, prevents bit line breakage due to agglomeration, and ensures uniform formation of buried bit lines, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
barrier layers containing germanium to prevent metal silicide agglomeration
Implementation Method 2
since the vertical channel transistor and the buried bit line may be brought into direct contact with each other, a contact plug process is not required. Therefore, the parasitic capacitance of the bit line may be reduced.
Data Source
AI summary
A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.