Germanium Active Layer With Diffusion Barrier for Leakage Control
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Solution Overview
Problem
Conventional semiconductor devices face challenges in aligning metal gate electrodes with source and drain extension tips, leading to issues like punch-through and unwanted gate capacitance, and struggle with junction leakage, particularly in tri-gate transistors on bulk silicon substrates.
Innovation Solution
Incorporating a germanium active layer with an underlying diffusion barrier layer and a junction leakage suppression layer to control dopant diffusion and enhance etch selectivity, thereby improving alignment and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and process complexity is lowered, but junction leakage increases and alignment precision between gate electrode and source/drain extensions deteriorates
Solution Approach 1:
The patent divides the semiconductor structure into distinct functional layers: a silicon-germanium buffer layer stack (with multiple layers of varying composition) separated from the active channel region, and a diffusion barrier layer positioned between the source/drain extensions and the channel. This segmentation allows each layer to perform its specific function independently, suppressing leakage while maintaining manufacturability on bulk silicon substrates
Solution Approach 2:
The silicon-germanium buffer layer stack acts as an intermediary structure between the bulk silicon substrate and the active device region. This intermediate layer stack with graded composition provides a transition zone that prevents direct leakage paths while maintaining lattice matching, thus reducing junction leakage without requiring complete substrate replacement
2Reliability
If metal gate electrode depth is increased to improve gate control, then short-channel effects are reduced, but gate capacitance parasitics increase
Solution Approach 1:
The patent optimizes the depth and positioning parameters of the metal gate electrode relative to the source and drain extension tips. By precisely controlling these geometric parameters and the depth of the diffusion barrier layer, the design achieves effective gate control while limiting the formation of parasitic capacitance, balancing both requirements through parameter optimization
3Reliability
If source and drain extension tips are made deeper to prevent punch-through, then gate control is improved, but alignment precision requirements increase
Solution Approach 1:
The diffusion barrier layer is formed in advance at a predetermined position and depth before the source and drain extensions are created. This preliminary placement of the barrier layer establishes a reference structure that guides subsequent alignment steps, making the overall process more robust to alignment variations and reducing the stringency of precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses junction leakage, enables better gate control, and enhances etch selectivity, leading to improved performance and scalability of semiconductor devices.
Implementation Method 1
A diffusion barrier layer is disposed above the substrate, below the germanium active layer
Data Source
AI summary
Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.