Ge-rich Semiconductor Layers with Doped Transition Etch Suppression

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Solution Overview

Problem

The challenge in semiconductor technology is the difficulty in scaling germanium (Ge) features to sizes below 22 nm due to the material properties of Ge, particularly the challenge in etching SiGe layers without eroding the Ge active layer, which limits the performance gains in modern transistor designs.

Innovation Solution

The use of a p-type doped transition layer between the Ge-rich device layer and the silicon substrate enhances the resistance of the Ge-rich layer to etchants, allowing for selective etching of SiGe layers and preserving the fine Ge features, thereby enabling the fabrication of advanced semiconductor devices such as nanowire and nanoribbon structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If SiGe layers are etched to enable Ge active layer fabrication, then SiGe removal is achieved, but Ge active layer erosion occurs

Engineering Contradiction:
ImproveGe feature dimension controlVSAvoidGe layer erosion during SiGe etching
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

A thin transition layer (5-20 nm) of SiGe is introduced between the Ge-rich active layer and the bulk Si substrate. This intermediary layer serves as a buffer that protects the Ge active layer from direct contact with etchants during SiGe removal, thereby preventing Ge erosion while enabling selective SiGe etching to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The composition of the transition layer is specifically optimized to have lower Ge content (higher Si content) compared to the Ge-rich active layer above it. This parameter change in Ge concentration creates a compositional gradient that enables selective etching: etchants can remove the SiGe transition layer while leaving the Ge-rich active layer intact, thus resolving the erosion problem.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If Ge feature size is reduced for scaling, then device density increases, but etching selectivity becomes insufficient

Engineering Contradiction:
Improvedevice densityVSAvoidetch selectivity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements local quality variation through a graded SiGe buffer structure where the Ge content changes progressively from the substrate interface toward the Ge active layer. This creates zones with different etch resistances: the SiGe transition layer has lower Ge content and is more etch-selective, while the Ge-rich active layer maintains high Ge content for desired electrical properties. This local compositional differentiation enables sufficient etch selectivity even at scaled dimensions.

Inventive Principle:
Principle #3Local quality

3Reliability

If Ge-rich active layer is used for high performance, then charge carrier mobility improves, but etch resistance decreases

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidetch susceptibility
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The semiconductor structure is segmented into distinct functional layers: a Ge-rich active layer (with higher Ge content for optimal charge carrier mobility) and a separate SiGe transition layer (with lower Ge content for etch resistance). This segmentation allows each layer to be optimized for its specific function - the Ge-rich layer for electrical performance and the SiGe layer for fabrication robustness - without compromising either property.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the etch selectivity and resistance of Ge-rich layers, allowing for precise control of Ge feature dimensions and reducing sub-channel leakage, thus enabling the scaling of Ge-based transistors and improving their performance.

Implementation Method 1

a p-type doped transition layer between the Ge-rich device layer and the silicon substrate enhances the resistance of the Ge-rich layer to etchants

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS10008565B2Semiconductor devices with germanium-rich active layers and doped transition layers
Publication Date: 2018.06.26 INTEL CORP
  • US10008565B2 patent drawing
  • US10008565B2 patent drawing
  • US10008565B2 patent drawing

AI summary

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.