Germanium FET Capping Layer Void Prevention

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Solution Overview

Problem

Germanium-based FET transistors suffer from void formation during the germanidation process due to galvanic corrosion when in contact with more noble metals in aqueous solutions, as germanium oxide is water-soluble and lacks a passivating layer, unlike silicon-based transistors.

Innovation Solution

A capping layer, such as a SiGe layer, is applied on the germanium-based source and drain areas before the germanidation process to prevent exposure during the selective etch, with a portion reacting with the metal and another acting as an etch stop, minimizing void formation and protecting the underlying germanium from corrosion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a germanidation process is applied to reduce resistance of source/drain regions, then electrical conductivity is improved, but void formation occurs due to galvanic corrosion during wet etch

Engineering Contradiction:
Improveelectrical conductivityVSAvoidvoid formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A silicon oxide capping layer is introduced as an intermediary protective layer between the germanium and the aqueous etchant. This capping layer prevents direct contact between the germanium and the etching solution, thereby eliminating the galvanic corrosion that causes void formation while allowing the germanidation process to proceed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The silicon oxide capping layer is formed on the germanium surface before the germanidation and wet etch processes. This preliminary protective action prevents the harmful galvanic corrosion from occurring during subsequent processing steps, allowing the resistance reduction to be achieved without void formation

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If germanium is exposed to aqueous solutions during selective etch, then non-reacted metal is removed, but galvanic corrosion causes severe void formation

Engineering Contradiction:
Improvemetal removalVSAvoidvoid formation
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The silicon oxide capping layer serves as a mediator that allows the wet etch process to remove non-reacted metal while preventing the germanium from being exposed to the aqueous solution. The etchant can still access and remove the metal through or around the capping layer structure without causing galvanic corrosion

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The silicon oxide layer, which would normally be a barrier to etching, is utilized as a protective capping structure that actually enables the selective removal of metal while protecting the germanium. The capping layer geometry and properties are designed to allow beneficial metal removal while preventing harmful galvanic corrosion

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces or avoids void formation by preventing germanium exposure to aqueous solutions, ensuring a stable germanium-based channel and source/drain structure, allowing for improved manufacturing of germanium-based FET transistors with reduced resistance and enhanced device properties.

Implementation Method 1

performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

transforming at least part of the capping layer into a metal germano-silicide

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 3

preventing exposure of the germanium of the channel layer and source and drain areas during the selective removing (e.g. etch) of the non-consumed metal layer

Methodology Applied
Scientific EffectPhysical barrier protection: Physical Containment

Implementation Method 4

another, lower, unreacted part can function as an etch stop layer during the selective removing (e.g. etch) of the non-consumed metal layer

Methodology Applied
Scientific EffectEtch stop layer mechanism:

Data Source

PatentEP2704199B1Method of manufacturing a semiconductor device
Publication Date: 2020.01.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • EP2704199B1 patent drawingFigure 1
  • EP2704199B1 patent drawingFigure 2
  • EP2704199B1 patent drawingFigure 3

AI summary

A method for manufacturing a transistor device comprising a germanium based channel layer, the method comprising : - providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; - providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; - depositing a metal layer on the capping layer; - performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; - selectively removing non-consumed metal from the substrate by means of the predetermined etchant; - providing a premetal dielectric layer.