Germanium Fin Channel Structure Using ART for Defect Control
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Solution Overview
Problem
Conventional integrated circuit fabrication processes face challenges in scaling to the 10 nanometer node or smaller due to variability issues, leading to defects and inadequate film quality, particularly when growing silicon germanium or germanium on silicon substrates, which affects transistor performance.
Innovation Solution
The implementation of aspect ratio trapping (ART) by forming trenches in an isolation structure on a silicon substrate, where a germanium nucleation layer is grown to relax lattice defects, allowing for defect-free growth of silicon germanium or germanium layers, and a gate stack is formed on the exposed sidewalls of the fin structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling to 10 nanometer node or smaller, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability issues and defects
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming isolation trenches, growing silicon germanium fin structures, selectively removing portions, and forming gate electrodes. This segmentation allows each stage to be optimized independently, improving overall manufacturing precision while managing complexity through structured process breakdown
Solution Approach 2:
Isolation trenches are formed in advance before fin structure growth, and selective removal patterns are predetermined. These preliminary actions prepare the substrate and structures to receive subsequent layers with precise geometric control, ensuring high manufacturing precision at the 10 nanometer node
2Productivity
If silicon germanium or germanium layers are grown on silicon substrates, then device capacity is increased, but manufacturing precision deteriorates due to lattice mismatch defects
Solution Approach 1:
Different regions of the fin structure have different material compositions optimized for their specific functions. The silicon germanium or germanium layers are grown with controlled composition gradients and thickness variations to locally optimize carrier mobility where needed while maintaining lattice matching to reduce defects
Solution Approach 2:
A buffer layer or transition layer is introduced between the silicon substrate and the silicon germanium or germanium layers. This intermediary layer gradually transitions the lattice constant, reducing mismatch defects while enabling high-capacity device operation
3Quantity of substance
If feature size is reduced to 10 nanometer node or smaller, then device density is increased, but manufacturing precision deteriorates due to variability in fabrication processes
Solution Approach 1:
The patent employs precise control of deposition parameters, temperature, pressure, and gas flow rates during film formation. These parameter changes are optimized to achieve atomic-layer precision in film thickness and composition, enabling high device density while maintaining manufacturing precision at the 10 nanometer node and below
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the film quality of device layers, enhancing carrier mobility and transistor performance by reducing defects and lattice mismatch issues, enabling more efficient integration of non-lattice-matched materials in semiconductor fabrication.
Implementation Method 1
a germanium nucleation layer is grown to relax lattice defects, allowing for defect-free growth of silicon germanium or germanium layers
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.