Germanium FinFETs on Isolated Substrates for Leakage Reduction
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Solution Overview
Problem
Current semiconductor technologies face challenges in optimizing the performance of three-dimensional semiconductor devices, particularly in terms of isolation formation and electron/hole mobility, especially for germanium-based devices on silicon substrates, where existing methods struggle to achieve efficient substrate isolation and high mobility.
Innovation Solution
The method involves fabricating three-dimensional germanium-based semiconductor devices using a silicon-on-insulator (SOI) or under-fin-oxidation (UFO) approach, where germanium-containing FIN structures are formed on isolated substrates, allowing for gate-all-around or contact-all-around structures to improve short-channel performance and reduce leakage, using selective under-fin oxidation to isolate the devices from the bulk substrate and depositing SiGe or Ge materials with high germanium content for enhanced mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bulk silicon substrates are used for tri-gate transistor fabrication, then manufacturing cost is reduced and fabrication process is simplified, but device performance and short-channel behavior are degraded
Solution Approach 1:
The patent introduces an intermediary insulating layer (silicon dioxide) between the silicon substrate and the tri-gate transistor structure. This intermediary layer provides electrical isolation that improves short-channel behavior while allowing the use of bulk silicon substrates, thus maintaining manufacturing simplicity while achieving better device performance.
Solution Approach 2:
The patent segments the substrate into isolated regions using insulating material between adjacent transistors. This segmentation creates locally isolated substrates that prevent electrical interference between neighboring devices while maintaining the overall bulk silicon substrate structure, thereby improving short-channel behavior without complicating the overall fabrication process.
2Reliability
If silicon-on-insulator substrates are used for tri-gate transistor fabrication, then short-channel behavior is improved, but manufacturing cost increases and fabrication process becomes more complicated
Solution Approach 1:
The patent applies local quality by forming insulating layers only in specific regions where needed for isolation, rather than using global silicon-on-insulator substrates. This allows selective isolation between transistors while maintaining bulk silicon substrate properties in other areas, achieving improved short-channel behavior with reduced manufacturing complexity.
3Reliability
If global isolation is used in silicon-on-insulator substrates, then substrate isolation is achieved, but device density and integration are reduced
Solution Approach 1:
The patent uses segmentation to create local isolation regions between individual transistors or small groups of transistors, rather than applying global isolation across the entire substrate. This segmented approach provides necessary substrate isolation while leaving other regions available for additional devices, thereby maintaining high device density and integration.
Solution Approach 2:
The patent implements local quality by providing isolation only where specifically needed between adjacent devices, rather than uniform global isolation. This allows maximum device density in regions where isolation is not required, while ensuring proper electrical isolation where devices are placed in close proximity.
4Ease of manufacture
If conventional isolation techniques are used for three-dimensional isolated channel devices, then fabrication is achieved, but isolation efficiency and device performance are insufficient
Solution Approach 1:
The patent introduces an intermediary insulating layer as a mediator between the silicon substrate and the three-dimensional channel structures. This intermediary silicon dioxide layer provides efficient electrical isolation that prevents leakage currents while being compatible with conventional fabrication processes, thus achieving both ease of manufacture and high isolation efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of tri-Gate and FIN-FET transistors by improving hole carrier mobility and reducing leakage, making them suitable for smaller node generations like the 14 nanometer node and beyond, while also minimizing gate-induced drain leakage and junction leakage.
Implementation Method 1
The silicon layer is oxidized to form silicon dioxide
Data Source
Figure 1A~1C
Figure 1D~1F
Figure 1G~1I
AI summary
Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.