Germanium Thin Film Local Interconnects for 3D CMOS
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Solution Overview
Problem
The interconnection between silicon CMOS and germanium CMOS devices is difficult to fabricate, limiting device density in known silicon-germanium CMOS structures.
Innovation Solution
A method involving the deposition of a germanium thin film on a silicon substrate, followed by rapid thermal annealing to form single-crystal or polycrystalline germanium layers, which are then used to create local interconnects between silicon and germanium CMOS devices, utilizing seed windows and dielectric encapsulation to facilitate direct contact and epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is provided to separate silicon CMOS from germanium CMOS, then device separation is achieved, but interconnection fabrication becomes difficult
Solution Approach 1:
The patent divides the interconnection structure into multiple segments: a first conductive layer for local interconnect, a second conductive layer for global interconnect, and intermediate dielectric layers. This segmentation allows each layer to be optimized independently, making fabrication easier while maintaining device separation
Solution Approach 2:
The patent introduces an intermediate dielectric layer with a via hole that mediates between the separated silicon CMOS and germanium CMOS devices. This intermediary structure provides a controlled pathway for interconnection while preserving the beneficial separation between different device types
2Ease of manufacture
If conventional interconnection methods are used, then fabrication process is simple, but device density is limited
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional stacked interconnection by adding vertical conductive layers above the dielectric layer. This dimensional change enables multiple interconnect levels, significantly increasing device density while maintaining compatibility with conventional fabrication processes
Solution Approach 2:
The patent implements nested conductive structures where the second conductive layer is positioned above and surrounds portions of the first conductive layer, creating a nested arrangement that maximizes interconnection density within the available vertical space
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the easy fabrication of local interconnects between silicon and germanium CMOS devices, increasing device density and allowing for the construction of high-density 3D CMOS structures such as SRAM cells with reduced resistance and contact issues.
Implementation Method 1
rapid thermal annealing the wafer and the layers formed thereon at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition
Implementation Method 2
cooling to solidify the germanium as single crystal germanium and as polycrystalline germanium
Implementation Method 3
Liu et al., High quality single-crystal Germanium on insulator by liquid-phase epitaxy on Silicon substrate
Data Source
AI summary
A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.